This paper proposes a method of short-range indoor localization using differential phase measurements of synchronized two-tone ultrasonic signals in an Orthogonal Frequency Multiple Access (OFDMA) scheme. This indoor positioning system (IPS) operates at an ultrasonic frequency of approximately 40kHz and synchronizes using an infrared signal. The OFDMA scheme allows for a receiver to process the signals from multiple transmitters continuously without the signals interfering with each other. The phases of the signals are measured using Goertzel Filters, allowing for low-complexity frequency content analysis. A MATLAB simulation using the proposed localization method is performed using four transmitter nodes in the corners of a 2.5m x 2.5m room and a receiver node within. The designs for the synchronizing transmitter node and the receiver node are then implemented in hardware and tested at 22cm and 28cm. The work described in this paper found that the proposed IPS functions correctly in simulation, and the hardware implementation of the receiver and transmitter provides accurate distance measurements with variance as low as 0.05cm. This variance is on the same order of magnitude as the wavelength of the ultrasonic signals used. The hardware used in the implementation of this design is low-power, low-cost, and easy to implement, but it carries with it design tradeoffs. The main difficulty introduced by the hardware is the generation of imperfectly orthogonal signals due to a time-discretization error imposed by the clock of the transmitter's general purpose microcontroller. This error is theoretically and experimentally analyzed yielding closely matching values.

Falls in the disabled and elderly people have been a cause of concern as they can be immobilized by the fall and have no way to contact others and seek assistance. The proposed frequency modulated continuous wave (FMCW) short range radar (SRR) system, which uses ultra-wideband (UWB) signals can provide immediate assistance by monitoring and detecting fall events. The unique characteristics of this system allow for a frequency-based modulation system to carry out triangulation and sense the location of the fall through the usage of a continuous chirp signal that linearly sweeps frequency. This project focuses on the development, design and simulation of a ring oscillator that exhibits the frequency modulated signal on a single integrated circuit chip. The ring oscillator is controlled by a voltage ramp signal generator and a voltage to current (V-I) converter. The circuit is designed in Cadence using TSMC 180nm process technology and operates in the frequency range of 3.409 GHz to 5.349 GHz with a spectral bandwidth of 1.94 GHz, which meets the Federal Communications Commission’s standards for unlicensed ultra-wideband transmissions.

This project investigates the failure of various CMOS circuits as a result of Time Dependent Dielectric Breakdown (TDDB) and explores design techniques to increase the mean time to failure (MTTF) of large-scale circuits. Time Dependent Dielectric Breakdown is a phenomenon where the oxide underneath the gate degrades as a result of the electric field in the material. Currently, there are few well documented design techniques that can increase lifetime, but with a tool chain I created called the MTTF Analyzing Program, or MAP, I was able to test circuits under various conditions in order to identify weak links, discover relationships, and reiterate on my design and see improvements and effects. The tool chain calculates power consumption, performance, temperature, and MTTF for a 'real life' circuit. Electric VLSI, an Electronic Design Automation tool, outputs a Spice file that yields parasitic quantities and spatial dimensions. LTspice, a high performance Spice simulator, was used to calculate the voltage and current data. Finally, I created MAP to monitor the voltage, current, and dimension data and process that in conjunction with HotSpot, a thermal modeling tool, to calculate a MTTF for each MOSFET. Analysis of the data from the software infrastructure showed that transistor sizing played a role in the MTTF. To maximize the MTTF of a transistor in a CMOS inverter, the activity of the pull-up transistor should be balanced with the transistor in the pull-down chain, ensuring the electric fields are balanced across both transistors. While it is impossible to completely balance an arbitrary CMOS circuit's activity for an arbitrary set of input signals, circuits can be intelligently skewed to help maximize the MTTF without increasing power consumption and without sacrificing circuit performance. Consequently, attaining a maximum MTTF does not come at a cost as it is possible to design a circuit with a high MTTF that performs better and uses less power than a circuit with low MTTF.

Chiplets have become an increasingly popular technology for extending Moore's Law and improving the reliability of integrated circuits. They do this by placing several small, interacting chips on an interposer rather than the traditional, single chip used for a device. Like any other type of integrated circuit, chiplets are in need of a physical layer of security to defend against hardware Trojans, counterfeiting, probing, and other methods of tampering and physical attacks. Power distribution networks are ubiquitous across chiplet and monolithic ICs, and are essential to the function of the device. Thus, we propose a method of fingerprinting transient signals within the PDN to identify individual chiplet systems and physical-layer threats against these devices. In this work, we describe a Python-wrapped HSPICE model we have built to automate testing of our proposed PDN fingerprinting methods. We also document the methods of analysis used- wavelet transforms and time-domain measurements- to identify unique characteristics in the voltage response signals to transient stimuli. We provide the true positive and false positive rates of these methods for a simulated lineup of chips across varying operating conditions to determine uniqueness and reliability of our techniques. Our simulations show that, if characterized at varying supply voltage and temperature conditions in the factory, and the sensors used for identification meet the sample rates and voltage resolutions used in our tests, our protocol provides sufficient uniqueness and reliability to be enrolled. We recommend that experimentation be done to evaluate our methods in hardware and implement sensing techniques to meet the requirements shown in this work.

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As the scaling of CMOS approaches fundamental limits, revolutionary technology beyond the end of CMOS roadmap is essential to continue the progress and miniaturization of integrated circuits. Recent research efforts in 3-D circuit integration explore pathways of continuing the scaling by co-designing for device, circuit, connectivity, heat and manufacturing challenges in a 3-D fabric-centric manner. SkyBridge fabric is one such approach that addresses fine-grained integration in 3-D, achieves orders of magnitude benefits over projected scaled 2-D CMOS, and provides a pathway for continuing scaling beyond 2-D CMOS. However, SkyBridge fabric utilizes only single type transistors in order to reduce manufacture complexity, which limits its circuit implementation to dynamic logic. This design choice introduces multiple challenges for SkyBridge such as high switching power consumption, susceptibility to noise, and increased complexity for clocking. In this thesis we propose a new 3-D fabric, similar in mindset to SkyBridge, but with static logic circuit implementation in order to mitigate the afore-mentioned challenges. We present an integrated framework to realize static circuits with vertical nanowires, and co-design it across all layers spanning fundamental fabric structures to large circuits. The new fabric, named as SkyBridge-CMOS, introduces new technology, structures and circuit designs to meet the additional requirements for implementing static circuits. One of the critical challenges addressed here is integrating both n-type and p-type nanowires. Molecular bonding process allows precise control between different doping regions, and novel fabric components are proposed to achieve 3-D routing between various doping regions. Core fabric components are designed, optimized and modeled with their physical level information taken into account. Based on these basic structures we design and evaluate various logic gates, arithmetic circuits and SRAM in terms of power, area footprint and delay. A comprehensive evaluation methodology spanning material/device level to circuit level is followed. Benchmarking against 16nm 2-D CMOS shows significant improvement of up to 50X in area footprint and 9.3X in total power efficiency for low power applications, and 3X in throughput for high performance applications. Also, better noise resilience and better power efficiency can be guaranteed when compared with original SkyBridge fabrics.

Recent developments in machine learning and artificial intelligence have sparked an influx of workloads that require specialized computer hardware for cloud services. The hardware running machine learning models predominantly consists of graphics processing units (GPUs) and tensor processing units (TPUs). However, these com- ponents are expensive for cloud services to purchase, costly for customers to rent, prone to price spikes, and energy-intensive. In this research we show that both cloud services and customers would benefit from utilizing field programmable gate arrays (FPGAs) to alleviate the aforementioned challenges. An FPGA can be configured as a machine learning accelerator, operating similarly to a GPU or TPU. We propose an FPGA-based architecture that utilizes compressed neural networks. This provides an alternative hardware option for those running machine learning inference, resulting in savings in server construction costs, power consumption, workload distribution, and providing a more affordable option for customers. We evaluate the system using architectural simulations and cloud-based deployment and demonstrate 76.2% cost and 26.5% energy savings on average from using the Neural Compression Inference Accelerator (NCIA).

Les automates cellulaires, composes d'un grand nombre de processeurs élémentaires, permettent un traitement rapide et efficace de certaines algorithmes. Le présent travail étudie la possibilité d'une implantation parallèle d'un tel automate sur un circuit intégré avec des entrées optiques en utilisant des photodiodes intégrées et un illuminateur de tableaux et des sorties optoélectroniques avec des modulateurs a puits quantiques multiples. Différents composants ont été étudiés et réalisés dans ce but: illuminateur de tableaux réalisé sur un hologramme en utilisant l'effet d'imagerie de talbot. Une amélioration des aberrations chromatiques est proposée en changeant les conditions d'enregistrement; circuit électronique intégrée VLSI contenant un seul processeur élémentaire avec des photodiodes intégrées pour les entrées optiques et les plots de sortie spéciaux pour les modulateurs; modulateurs opto-électroniques a puits quantiques multiples. Un montage expérimental a été réalisé en éclairant une photodiode avec une diode laser a 999 nm. L'estimation des performances de l'automate propose montre sa haute capacité de calcul et de connexion.