Analytic and force-directed placement methods that simultaneously minimize wire length and spread cells are receiving renewed attention from both academia and industry. However, these methods are by no means trivial to implement---to date, published works have failed to provide sufficient engineering details to replicate results. This dissertation addresses the implementation of a generic force-directed placer entitled FDP. Specifically, this thesis provides (1) a description of efficient force computation for spreading cells, (2) an illustration of numerical instability in this method and a means to avoid the instability, (3) metrics for measuring cell distribution throughout the placement area, and (4) a complementary technique that aids in minimizing wire length. FDP is compared to Kraftwerk and other leading academic tools including Capo, Dragon, and mPG for both standard cell and mixed-size circuits. Wire lengths produced by FDP are found to be, on average, up to 9% and 3% better than Kraftwerk and Capo, respectively. All told, this thesis confirms the validity and applicability of the approach, and provides clarifying details of the intricacies surrounding the implementation of a force-directed global placer.

It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm. It draws out the limits encountered by the existing implementation for both FPGA and VLSI realizations. A rather unconventional adoption of the carry-save representation combined with a soft-threshold comparison is proposed to circumvent these limitations. The resulting design is described and evaluated. Mathematically appealing results on the quality of the approximation achieved by this approach are presented. The underlying proofs and technical details are provided in the appendix.

Engineers often view variability as undesirable and seek to minimize it, such as when they employ transistor-matching techniques to improve circuit and system performance. Biology, however, makes no discernible attempt to avoid this variability, which is particularly evident in biological nervous systems whose neurons exhibit marked variability in their cellular properties. In previous studies, this heterogeneity has been shown to have mixed consequences on network rhythmicity, which is essential to locomotion and other oscillatory neural behaviors. The systems that produce and control these stereotyped movements have been optimized to be energy efficient and dependable, and one particularly well-studied rhythmic network is the central pattern generator (CPG), which is capable of generating a coordinated, rhythmic pattern of motor activity in the absence of phasic sensory input. Because they are ubiquitous in biological preparations and reveal a variety of physiological behaviors, these networks provide a platform for studying a critical set of biological control paradigms and inspire research into engineered systems that exploit these underlying principles. We are directing our efforts toward the implementation of applicable technologies and modeling to better understand the combination of these two concepts---the role of heterogeneity in rhythmic networks of neurons. The central engineering theme of our work is to use digital and analog platforms to design and build Hodgkin--Huxley conductance-based neuron models that will be used to implement a half-center oscillator (HCO) model of a CPG. The primary scientific question that we will address is to what extent this heterogeneity affects the rhythmicity of a network of neurons. To do so, we will first analyze the locations, continuities, and sizes of bursting regions using single-neuron models and will then use an FPGA model neuron to study parametric and topological heterogeneity in a fully-connected 36-neuron HCO. We found that heterogeneity can lead to more robust rhythmic networks of neurons, but the type and quantity of heterogeneity and the population-level metric that is used to analyze bursting are critical in determining when this occurs.

Power supply noise has become a critical issue for low power and high performance circuit design in recent years. The rapid scaling of the CMOS process has pushed the limit further and further in building low-cost and increasingly complex digital VLSI systems. Continued technology scaling has contributed to significant improvements in performance, increases in transistor density, and reductions in power consumption. However, smaller feature sizes, higher operation frequencies, and supply voltage reduction make current and future VLSI systems more vulnerable to power supply noise. Therefore, there is a strong demand for strategies to prevent problems caused by power supply noise. Design challenges exist in different design phases to reduce power supply noise. In terms of physical design, careful power distribution design is required, since it directly determines the quality of power stability and the timing integrity. In addition, power management, such as switching mode of the power gating technique, is another major challenge during the circuit design phase. A bad power gating switching strategy may draw an excessive rush current and slow down other active circuitry. After the circuit is implemented, another critical design challenge is to estimate power supply noise. Designers need to be aware of the voltage drop in order to enhance the power distribution network without wasting unnecessary design resources. However, estimating power supply noise is usually difficult, especially finding the circuit activity which induces the maximum supply noise. Blind search may be very time consuming and not effective. At post-silicon test, detecting power supply noise within a chip is also challenging. The visibility of supply noise is low since there is no trivial method to measure it. However, the supply noise measurement result on silicon is critical to debug and to characterize the chip. This dissertation focuses on novel circuit designs and design methodologies to prevent problems resulted from power supply noise in different design phases. First, a supply noise estimation methodology is developed. This methodology systematically searches the circuit activity inducing the maximum voltage drop. Meanwhile, once the circuit activity is found, it is validated through instruction execution. Therefore, the estimated voltage drop is a realistic estimation close to the real phenomenon. Simulation results show that this technique is able to find the circuit activity more efficiently and effectively compared to random simulation. Second, two on-chip power supply noise detectors are designed to improve the visibility of voltage drop during test phase. The first detector facilitates insertion of numerous detectors when there is a need for additional test points, such as a fine-grained power gating design or a circuit with multiple power domains. It focuses on minimizing the area consumption of the existing detector. This detector significantly reduces the area consumption compared to the conventional approach without losing accuracy due to the area minimization. The major goal of designing the second on-chip detector is to achieve self-calibration under process and temperature variations. Simulation and silicon measurement results demonstrate the capability of self-calibration regardless these variations. Lastly, a robust power gating reactivation technique is designed. This reactivation scheme utilizes the on-chip detector presented in this dissertation to monitor power supply noise in real time. It takes a dynamic approach to control the wakeup sequence according to the ambient voltage level. Simulation results demonstrate the ability to prevent the excessive voltage drop while the ambient active circuitry induces a high voltage drop during the wakeup phase. As a result, the fixed design resource, which is used to prevent the voltage emergency, can potentially be reduced by utilizing the dynamic reactivation scheme. / text

Στη παρούσα διδακτορική διατριβή του κ. Χαράλαμπου Μιχαήλ με τίτλο «Βελτιστοποίηση Επαναπροσδιοριζόμενων Αρχιτεκτονικών για Απόδοση και Κατανάλωση Ενέργειας για Κρυπτογραφικές Εφαρμογές και Εφαρμογές Κυριαρχούμενες από Δεδομένα» προτείνονται, αναπτύσσονται και μελετώνται αποδοτικές τεχνικές βελτιστοποίησης της απόδοσης ή/και της κατανάλωσης ενέργειας για κρυπτογραφικές εφαρμογές καθώς και εφαρμογές κυριαρχούμενες από δεδομένα που υλοποιούνται σε ενσωματωμένες πλατφόρμες ειδικού σκοπού. Συνολικά, οι προτεινόμενες τεχνικές μελετήθηκαν για τις διάφορες παραμέτρους που έχουν και συνολικά οδήγησαν στην διαμόρφωση της προτεινόμενης γενικής μεθοδολογίας βελτιστοποίησης των κρυπτογραφικών και λοιπών εφαρμογών κυριαρχούμενων από δεδομένα. Τα θεωρούμενα συστήματα στοχεύουν σε αριθμητικά απαιτητικές εφαρμογές και προέκυψαν εντυπωσιακές βελτιστοποιήσεις ειδικά δε στην απόδοση συγκεκριμένων κρυπτογραφικών εφαρμογών όπως οι συναρτήσεις κατακερματισμού και ανάμειξης (hash functions) και κατά συνέπεια και των αντίστοιχων κρυπτογραφιών μηχανισμών στους οποίους αυτές χρησιμοποιούνται. Πρωταρχικός σχεδιαστικός στόχος είναι η αύξηση της ρυθμαπόδοσης σχεδιάζοντας κρυπτογραφικές εφαρμογές για διακομιστές υπηρεσιών ή γενικότερα εφαρμογές κυριαρχούμενες από δεδομένα. Λαμβάνοντας επίσης υπόψη το γεγονός ότι η κρυπτογραφία αποτελεί σήμερα –πιο πολύ παρά ποτέ- ένα αναγκαίο και αναντικατάστατο συστατικό της ανάπτυξης ηλεκτρονικών υπηρεσιών μέσω διαδικτύου και της εν τέλει μετάβασης της ανθρωπότητας στο νέο οικονομικό μοντέλο της «ηλεκτρονικής οικονομίας» είναι προφανής η σημασία της προτεινόμενης μεθοδολογίας και των αντίστοιχων σχεδιασμών που προκύπτουν. Η ολοκλήρωση των κρυπτογραφικών συστημάτων ασφαλείας σε υλικό είναι σχεδόν αναγκαία για τα ενσωματωμένα συστήματα κρυπτογράφησης. Τα πλεονεκτήματα που έχουμε είναι η υψηλή απόδοση, η μειωμένη κατανάλωση ισχύος με μειονέκτημα το κόστος της ολοκλήρωσης σε υλικό. Νέες τεχνολογίες όπως FPGAs (Field-Programmable Gate Array), επιτρέπουν την πιο εύκολη ολοκλήρωση του αλγορίθμου και την ανανέωση - αντικατάστασή του από νεώτερους-βελτιωμένους. Ήδη τα τελευταίας γενιάς FPGAs τείνουν να έχουν τις ιδιότητες των ASICs (Application-Specific Integrated Circuit) -μειωμένη κατανάλωση ισχύος, υψηλή απόδοση, και ρύθμιση της λειτουργικότητας ανάλογα την εφαρμογή. Ένα άλλο πλεονέκτημα των υλοποιήσεων σε υλικό είναι πως από την φύση τους είναι λιγότερο ευαίσθητο σε επιθέσεις κρυπτανάλυσης ενώ μπορούν ευκολότερα να ενσωματώσουν πολιτικές αντιμετώπισης κρυπταναλυτικών τεχνικών . Ερευνητική Συνεισφορά Ανάπτυξη και μελέτη τεχνικών βελτιστοποίησης που οδηγούν σε σχέδια με πολύ υψηλή ρυθμαπόδοση και περιορισμένο κόστος σε επιφάνεια ολοκλήρωσης για κρυπτογραφικές και υπολογιστικά απαιτητικές εφαρμογές Αναπτύσσονται και αναλύονται όλες οι επιμέρους τεχνικές που αξιολογήθηκαν κατά την εκπόνηση της εν λόγω διδακτορικής διατριβής και χρησιμοποιούνται για την βελτιστοποίηση των σχεδίων σε υλικό. Μελετώνται οι παράμετροι εφαρμογής ανάλογα με την υφή της κάθε τεχνικής και τα τιθέμενα σχεδιαστικά κριτήρια, τα οποία εξαρτώνται από τα επιθυμητά χαρακτηριστικά των σχεδίων σε υλικό καθώς και από τις εν γένει προδιαγραφές τους ανάλογα με τον εκάστοτε σχεδιαστικό στόχο. Ανάπτυξη και μελέτη «πάνω-προς-τα-κάτω» μεθοδολογίας βελτιστοποίησης των σχεδίων που οδηγούν σε πολύ υψηλή ρυθμαπόδοση και περιορισμένο κόστος σε επιφάνεια ολοκλήρωσης για κρυπτογραφικές και υπολογιστικά απαιτητικές εφαρμογές Αναπτύσσεται ολοκληρωμένη και δομημένη συνολική μεθοδολογία βελτιστοποίησης σχεδίων, με βάση τις επιμέρους τεχνικές που παρουσιάστηκαν και αναλύθηκαν, που οδηγεί σε γενική μεθοδολογία η οποία είναι εφαρμόσιμη σε όλες σχεδόν τις συναρτήσεις κατακερματισμού για τις οποίες καταφέρνει να παράγει σχέδια υψηλής απόδοσης με περιορισμένο κόστος σε επιφάνεια ολοκλήρωσης. Ταυτόχρονα, αναλύονται τα θεωρητικώς αναμενόμενα οφέλη από την κάθε επιμέρους τεχνική βελτιστοποίησης καθώς και από την συνολική εφαρμογή της μεθοδολογίας βελτιστοποίησης του σχεδιασμού σε υλικό ανάλογα με την επιλεχθείσα τιμή των παραμέτρων της κάθε εφαρμοζόμενης τεχνικής. Ανάπτυξη σχεδίων σε υλικό πολύ υψηλής βελτιστοποίησης για τις συναρτήσεις κατακερματισμού SHA-1 και SHA-256 Παρουσιάζεται η διαδικασία βελτιστοποίησης του σχεδιασμού σε υλικό των δυο πιο σημαντικών συναρτήσεων κατακερματισμού αναφέροντας σε κάθε περίπτωση τα επιμέρους κέρδη, καθώς και την συνολική βελτίωση που επιτεύχθηκε με την εφαρμογή της προτεινόμενης μεθοδολογίας. Οι δύο συναρτήσεις είναι οι SHA-1 (η πιο δημοφιλής συνάρτηση κατακερματισμού στις σημερινές εφαρμογές) και SHA-256 (που αναμένεται να χρησιμοποιηθεί ευρύτατα στο μέλλον παρέχοντας υψηλότερο επίπεδο ασφάλειας). Υλοποιήσεις σε συγκεκριμένες επαναπροσδιοριζόμενες αρχιτεκτονικές συγκρίνονται με αντίστοιχες που έχουν προταθεί ερευνητικά ή είναι εμπορικά διαθέσιμες, αποδεικνύωντας την υπεροχή των προτεινόμενων σχεδίων. Έτσι προκύπτουν σχέδια πολύ υψηλής ρυθμαπόδοσης (τουλάχιστον 160% βελτιωμένοι σε σχέση με συμβατικές υλοποιήσεις) με περιορισμένο κόστος σε επιφάνεια ολοκλήρωσης (λιγότερο από 10% σε επίπεδο συνολικού κρυπτογραφικού συστήματος στην χειρότερη περίπτωση σε σχέση με συμβατικές υλοποιήσεις), βελτιστοποιώντας τον σχεδιαστικό παράγοντα «απόδοση x επιφάνεια ολοκλήρωσης» σε σχέση με άλλες εμπορικές ή ακαδημαϊκές υλοποιήσεις. / In this Ph.D dissertation, certain design techniques and methodologies, for various hardware platforms, aiming to boost performance of cryptographic modules and data intensive applications are presented. This way we manage to obtain hardware designs with extremely high throughput performing much better that anyone else that has been previously proposed either by academia or industry. Taking in consideration the rapid evolution of e-commerce and the need to secure all kind of electronic transactions, it is obvious that there is a great need to achieve much higher throughputs for certain cryptographic primitives. Especially in IPv6, HMAC etc it is crucial to design hash functions that achieve the highest degree of throughput since hashing is the limiting factor in such security schemes. The proposed methodology achieves to tackle this problem achieving to offer design solutions for hashing cores that can increase their throughput up to 160%. The proposed methodology is generally applicable to all kind of hash functions and this is a main characteristic of its importance. The proposed techniques and methodologies go far beyond from just unrolling the rounds of the algorithm and/or using extended pipelining techniques. It offers an analysis on these techniques while at the same time proposes some new, which all together form a holistic methodology for designing high-throughput hardware implementations for hash functions or other data intensive applications. These designs that can achieve high throughput rates are appropriate for high-end applications that are not constrained in power consumption and chip covered area. The main contributions of this PhD thesis involve: Developing and study of certain optimizing techniques for increasing throughput in cryptographic primitives and data intensive applications Certain design techniques that can take part in a generic methodology for improving hardware performance characteristics are proposed and studied. This study has been conducted in terms of each technique’s parameters and certain design criteria are mentioned in order to choose their values. These design criteria depend on the intended hardware characteristics, specifications and available hardware resources for the cryptographic primitive or data intensive application. Developing and study of top-down methodology for increasing throughput in cryptographic primitives and data intensive applications Techniques that were previously proposed and analyzed are merged in order to form propose a top-down methodology able to boost performance of cryptographic primitives and data intensive applications. Design parameters are studied in order to propose various design options with the default one being achieving the highest degree of throughput maintaining the best throughput/area ratio. The proposed methodology can significantly increase throughput of hardware designs leading theoretically even to 160% increase of throughput with less than 10% cost in integration area for the whole cryptographic system. Highly optimized hardware designs for the two main hash functions: SHA-1 and SHA-256 with high-throughput properties. In this contribution high throughput designs and implementations are proposed concerning the two most widely used hash functions SHA-1 and SHA-256. SHA-1 is currently the most widely deployed hashing function whereas SHA-256 has started to phase out SHA-1 due to security issues that have recently been reported. These two designs also serve as case studies for the application of the proposed methodology aiming to increase throughput in cryptographic modules and data intensive applications. Our implementation does not only increases throughput by a large degree, but it also utilizes limited area resources thus offering an advantageous "throughput x area" product in comparison with other hashing cores implementations, proposed either by academia or industry. The proposed design achieves maximum throughput over 4.7 Gbps for SHA-1 and over 4.4 Gbps for SHA-256 in Xilinx Virtex II platform with minor area penalty comparing to conventional implementations. These synthesis results are only slightly decreased after the place-and-route procedure

The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power. In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel readout implementation in CMOS image sensors is presented. The aim of the conducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the performance of the carried-out design have been analyzed. As an architectural improvement possibility two MDAC capacitor mismatch error reduction techniques have been presented.

Les nanotubes de carbone (NTC) possèdent des propriétés électriques pouvant répondre aux futures demandes de la microélectronique. Toutefois, des méthodes d'intégration de ces nano-objets dans des systèmes complexes doivent être développées. Le but de ces travaux de thèse était le développement d'un procédé permettant de déposer sélectivement des NTC doubles parois de manière orientée, et ce, à l'échelle d'un wafer de silicium. Un certain nombre de méthodes ont été développées. L'utilisation d'une pulvérisation de suspension de NTC couplée à différentes méthodes de microstructuration a permis de réaliser, à de grandes échelles, des dépôts de tapis de NTC microstructurés à des résolutions de l'ordre du micron. Bien que ne répondant pas à tous les critères requis pour la microélectronique ces techniques de dépôt ont pu trouver une application dans le domaine de l'ingénierie tissulaire. Ces travaux ont donné lieu à un dépôt de brevet. Afin d'améliorer les méthodes de synthèse de nos échantillons de NTC conducteurs, une technique de caractérisation grande échelle des caractéristiques électriques de NTC a été mise en œuvre. En effet, l'impossibilité d'obtenir une information statistique sur les propriétés des NTC présents dans un échantillon entravait les possibilités d'optimisation. La technique développée se base sur l'étude de la réponse d'un ensemble de NTC soumis à une forte rampe de tension. La destruction successive des NTC permet de mesurer les propriétés de nano-objets individuels et ainsi de rapidement tirer des données statistiques. Finalement, une technique originale basée sur la manipulation de NTC par des champs électriques et des forces capillaires a été développée. Le contrôle des forces capillaires permet de concentrer des NTC dans une cavité où ces derniers seront piégés et alignés par un champ électrique. Cette technique a permis non seulement d'obtenir des connexions en NTC denses et très conductrices mais également de réaliser dive rs dispositifs fonctionnels tels que des nano-résonateurs ou encore des capteurs.

Optimization theory is a key technology for inverse problems of reconstruction in science, engineering and economy. Discrete tomography is a modern research field dealing with the reconstruction of finite objects in, e.g., VLSI chip design, where this thesis will focus on. In this work, a framework with its supplementary algorithms and a new problem reformulation are introduced to approximately resolve this NP-hard problem. The framework is modular, so that other reconstruction methods, optimization techniques, optimal experimental design methods can be incorporated within. The problem is being revisited with a new optimization formulation, and interpretations of known methods in accordance with the framework are also given. Supplementary algorithms are combined or incorporated to improve the solution or to reduce the cost in terms of time and space from the computational point of view.

Esta tese objetiva propor algorítmos para a redução do tamanho dos fios em circuitos VLSI considerando elementos críticos dos circuitos. O problema é abordado em duas perspectivas diferentes: posicionamento e roteamento. Na abordagem de posicionamento, a tese explora métodos para realizar posicionamento de um tipo particular de circuito VLSI, que são conhecidos como circuitos 3D. Diferente de trabalhos anteriores, este tese aborda o problema considerando as conexões verticais (chamadas 3D-Vias) e as limitações impostas pelas mesmas. Foi realizado um fluxo completo, iniciando no tratamento de pinos de entrada e saída (E/S), posicionamento global, posicionamento detalhado e posicionamento das 3D-Vias. A primeira etapa espalha os pinos de E/S de maneira equilibrada objetivando auxiliar o posicionamento para obter uma quantidade reduzida de 3D-Vias. O mecanismo de posicionamento global baseado no algorítmo de Quadratic Placement considera informações da tecnologia e requerimento de espaçamento de 3D-Vias para reduzir o comprimento das conexões e equilibrar a distrubuição das células em 3D. Conexes críticas podem ser tratadas através da insercão de redes artificiais que auxiliam a evitar que 3D-Vias sejam usadas em conexões críticas do circuito. Finalmente, 3D-Vias são posicionadas por um algorítmo rápido baseado na legalizaçãao Tetris. O framework completo reforça os potenciais benefícios dos circuitos 3D para a melhora do comprimento das conexões e apresenta algorítmos eficientes projetados para circutos 3D podendo estes serem incorporados em novas ferramentas. Na abordagem de roteamento, um novo algorítmo para obtenção de árvores de Steiner chamado AMAZE é proposto, combinando métodos existentes com novos métodos que são efetivos para produzir fios curtos e de baixo atraso para elementos críticos. Um técnica de biasing atua na redução do tamanho dos fios, obtendo resultados próximos da solução ótima enquanto que dois fatores de timing chamados path-length factor e sharing factor propiciam melhora do atraso para conexões sabidas como críticas. Enquanto que AMAZE apresenta melhorias significativas em um algorítmo padrão na indústria de CAD (Maze Routers), ele produz árvores de roteamento com uso de CPU comparável com algorítmos heurísticos de árvore de Steiner e menor atraso. / This thesis targets the wire length improvement of VLSI circuits considering critical elements of a circuit. It considers the problem from two different perspectives: placement and routing. On placement, it explores methods to perform placement of 3D circuits considering issues related to vertical interconnects (3D-Vias). A complete flow, starting from the I/O pins handling, global placement, detailed placement and 3D-Via placement is presented. The I/O pins algorithm spreads the I/Os evenly and aids the placer to obtain a reduced number of 3D-Vias. The global placement engine based on Quadratic algorithm considers the technology information and 3D-Via pitch to reduce wire length and balance the cells distribution on 3D. Critical connections can be handled by insertion of artificial nets that lead to 3D-Via avoidance for those nets. Finally, 3D-Vias are placed by a fast algorithm based on Tetris legalization. The whole framework enforces the potential benefits of 3DCircuits on wire length improvement and demonstrates efficient algorithms designed for 3D placement that can be incorporated in new tools. On routing, a new flexible Steiner tree algorithm called AMAZE is proposed, combining existing and new methods that are very effective to produce short wire length and low delay to critical elements. A biasing technique provides close to optimal wire lengths while a path length factor and a sharing factor enables a very wide delay and wire length trade-off. While AMAZE presents significant improvements on a industry standard routing algorithm (Maze Routers), it produces routing trees with comparable speed and beter delay than heuristic Steiner tree algorithms such as AHHK and P-Trees.

Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP). / This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).