Os projetistas de sistemas digitais enfrentam sempre o desafio de encontrar o balanço correto entre velocidade e generalidade de processamento de seu hardware. Originalmente dispositivos de lógica programável de alta densidade como FPGAs (Field Programable Gate Arrays) e CPLDs (Complex Logic Programmable Devices) vinham sendo utilizados como dispositivos de lógica acoplada(glue logic), reduzindo significantemente o número de componentes em um sistema. Seu uso como forma de substituir arquiteturas já existentes de microcontroladores e microprocessadores já é uma realidade. A representação e reconhecimento de objetos em imagens de duas dimensões é um tópico importante. Uma forma comum de se fazer a representação de um objeto ou uma imagem é a utilização de momentos da função de intensidade de um grupo de pixels. Devido ao alto custo computacional para o cálculo desses momentos tem sido importante a busca por arquiteturas que de alguma forma agilizem o cálculo dos mesmos. Um problema enfrentado por arquiteturas desenvolvidas atualmente para trabalhar em forma de periférico com um computador pessoal (PC) ou uma estação de trabalho é a velocidade do barramento de transferência de dados. Interfaces de uso mais simples, como USB (Universal Serial Bus) ou Ethernet, têm sua taxa de transferência na casa dos megabytes por segundo. Uma solução para esse problema é o uso do barramento PCI, as transferências feitas nesse barramento podem chegar à casa dos gigabytes por segundo. Esse trabalho vem apresentar uma arquitetura, em forma de soft core totalmente compatível com o padrão Wishbone, para a extração de características invariantes em imagens binárias utilizando-se de dispositivos de lógica programável complexa. Desse modo torna-se possível o uso do barramento PCI para a transmissão de dados para um microcomputador ou uma estação de trabalho. / A challenge for digital systems designers is to meet the balance between speed and flexibility was always. FPGAs and CPLDs where used as glue logic, reducing the number of components in a system. The use of programmable logic (CPLDs and FPGAs) as an alternative to microcontrollers and microprocessors is a real issue. Moments of the intensity function of a group of pixels have been used for the representation and recognition of objects in two dimensional images. Due to the high cost of computing the moments, the search for faster computing architectures is very important. A problem faced by nowadays developed architectures is the speed of computer communication buses. Simpler interfaces, as USB (Universal Serial Bus) and Ethernet, have their transfer rate in megabytes per second. A solution for this problem is the use the PCI bus, where the transfer rate can achieve gigabytes per second. This work presents a soft core architecture, fully compatible with the Wishbone standard, for the extraction of invariant characteristics from binary images using logic programmable devices.

Os projetistas de sistemas digitais enfrentam sempre o desafio de encontrar o balanço correto entre velocidade e generalidade de processamento de seu hardware. Originalmente dispositivos de lógica programável de alta densidade como FPGAs (Field Programable Gate Arrays) e CPLDs (Complex Logic Programmable Devices) vinham sendo utilizados como dispositivos de lógica acoplada(glue logic), reduzindo significantemente o número de componentes em um sistema. Seu uso como forma de substituir arquiteturas já existentes de microcontroladores e microprocessadores já é uma realidade. A representação e reconhecimento de objetos em imagens de duas dimensões é um tópico importante. Uma forma comum de se fazer a representação de um objeto ou uma imagem é a utilização de momentos da função de intensidade de um grupo de pixels. Devido ao alto custo computacional para o cálculo desses momentos tem sido importante a busca por arquiteturas que de alguma forma agilizem o cálculo dos mesmos. Um problema enfrentado por arquiteturas desenvolvidas atualmente para trabalhar em forma de periférico com um computador pessoal (PC) ou uma estação de trabalho é a velocidade do barramento de transferência de dados. Interfaces de uso mais simples, como USB (Universal Serial Bus) ou Ethernet, têm sua taxa de transferência na casa dos megabytes por segundo. Uma solução para esse problema é o uso do barramento PCI, as transferências feitas nesse barramento podem chegar à casa dos gigabytes por segundo. Esse trabalho vem apresentar uma arquitetura, em forma de soft core totalmente compatível com o padrão Wishbone, para a extração de características invariantes em imagens binárias utilizando-se de dispositivos de lógica programável complexa. Desse modo torna-se possível o uso do barramento PCI para a transmissão de dados para um microcomputador ou uma estação de trabalho. / A challenge for digital systems designers is to meet the balance between speed and flexibility was always. FPGAs and CPLDs where used as glue logic, reducing the number of components in a system. The use of programmable logic (CPLDs and FPGAs) as an alternative to microcontrollers and microprocessors is a real issue. Moments of the intensity function of a group of pixels have been used for the representation and recognition of objects in two dimensional images. Due to the high cost of computing the moments, the search for faster computing architectures is very important. A problem faced by nowadays developed architectures is the speed of computer communication buses. Simpler interfaces, as USB (Universal Serial Bus) and Ethernet, have their transfer rate in megabytes per second. A solution for this problem is the use the PCI bus, where the transfer rate can achieve gigabytes per second. This work presents a soft core architecture, fully compatible with the Wishbone standard, for the extraction of invariant characteristics from binary images using logic programmable devices.

This diploma thesis is focused on Formula Student upright analysis using final element method. The main goal is to review an effect of different boundary conditions on stress and deformation. Nowadays, the topologic optimization is a commonly used tool for design process of the upright, to create the lightest and the most rigid design possible. Boundary conditions, which should approximate reality really well, are one of inputs to topological optimization.

The trend of IP core reuse has been accelerating for years because of the increasing complexity in the System-on-Chip (SoC) designs. As a result, many IP cores of different types have been produced. Meanwhile, similar to the free software movement, an open core community has emerged because some designers choose to share their IP cores by using open source licenses. The open cores are growing fast due to their inherently attractive properties like accessible internal structure and usually no cost for license. Under this background, the master thesis was proposed by the company ENEA (Malmö/Lund branch), Sweden. It intended to evaluate the qualities of the open cores, as well as the difficulty and the feasibility of building an embedded platform by exclusively using the open cores. We contributed such an open core platform. It includes 5 open cores from the OpenCores organization: OpenRISC OR1200 processor, CONMAX WISHBONE interconnection IP core, Memory Controller IP core, UART16550, and General Purpose IOs (GPIO) IP core. More than that, we added the supports to DM9000A and WM8731 ICs for Ethernet and Audio features. On the software side, uC/OS-II RTOS and uC/TCP-IP stack have been ported to the platform. The OpenRISC toolchain for software development was tested. And a MP3 music player application has created to demonstrate the system. The open core platform is targeted to the Terasic’s DE2-70 board with ALTERA Cyclone II FPGA. It aims to have high flexibility for a wide range of embedded applications and at the same time with very low costs. The design of the thesis project are fully open and available online. We hope our work can be useful in the future as a starting point or a reference both for academic research or for commercial purposes.

FPGAs are commonly used in cloud computing due to their ability  to be  programmed  as a processor that serves a specific purpose; hence, achieving high performance at low power. On the other hand, FPGAs have a lot of resources available, which are wasted if they host a single application or serve a single user’s request. Partially Reconfiguration technology enables FPGAs to divide their resources into different regions and then dynamically reprogram those regions with various applications during runtime. Therefore, they are considered as a good solution to eliminate the underutilization resource problem. Nevertheless, the sizes of these regions are static; they cannot be increased or decreased once they are defined. Thereby, it leads to the underutilization of reconfigurable region resources. This thesis addresses this problem, i.e., how to dynamically increase/decrease partially reconfigurable FPGA resources matching an application’s needs. Our solution enables expanding and contracting the FPGA resources allocated to an application by 1) application acceleration requirements expressed in multiple smaller modules which are configured into multiple reconfigurable regions assigned to the application dynamically  and 2) providing a low - area - overhead, configurable, and isolated communication mechanism by adjusting crossbar interconnect and WISHBONE interface among those multiple reconfigurable regions. / FPGA - kretsar har en förmåga  att programmeras som processorer med ett specifikt syfte vilket gör att de ofta används i molnlösningar. Det tager hög prestanda med låg effektförbrukning. Å andra sidan disponerar FPGA - kretsar över stora resurser, vilka är bortkastade om de enbart används av en applikation eller endast på en användares förfrågan. Partiellt omkonfigurerbara teknologier tillåter FPGA - kretsar att fördela resurser mellan olika regioner, och sen dynamiskt omprogrammera regioner med olika applikationer vid körning. Därför betraktas partiellt omkonfigurerbara teknologier som en bra lösning för att minimera underutnyttjande av resurser. Storleken på regionerna är statiska och kan inte ändras när de väl definierats, vilket leder till underutnyttjande av de omkonfigurerbara regionernas resurser. Denna uppsats angriper problemet med dynamisk allokering av partiellt omkonfigurerbara FPGA - resurser utifrån applikationens behov. Vår lösning möjliggör ökning och minskning av FPGA - resurser allokerade till en applikation genom 1) accelerering av applikationen genom att applikationen tilldelas flera mindre moduler konfigurerade till dynamiskt omkonfigurerbara regioner, och 2) tillhanda hållande av en effektiv konfigurerbar och isolerad kommunikationsmekanism, genom justering av crossbar - sammankoppling en  och  WISHBONE - gränssnittet hos de omkonfigurerbara regionerna.

In the industry of intellectual property products "IP-cores", a communication link is almost always needed. A semiconductor intellectual property IP core is a reusable unit of logic in electronic design. IP cores are used as building blocks for ASIC chip design or FPGA logic designs. A bus creates a communication link between the IP cores in a system. The company AnaCatum Design AB have many projects where a bus is needed. Creating a new bus structure for every project is time consuming. By having a generic bus structure of a known standard with changeable parameters, the user only has to set the desired parameters to fit the system. Also having interfaces for master and slave the user has only to make minor changes to have a fully functional bus for the system.

The goal of this diploma thesis is to create structural design of reverse trike vehicle. With use of vehicle dynamics simulations in software MSC Adams Car 2019 is examining suitability of double wishbone suspension with different roll centre heights and effect of longitudinal position of Centre of mass on ride properties and limits. Selected concept of reverse trike vehicle is structurally designed using Solidworks 2016 and stress is inspected with FEM software Ansys Workbench 2019.

My diploma thesis is about project trailer bus for transportation of persons. It´s for SOR Libchavy spol. s r.o. This project work deals with four-wheel trailer bus for person transportation with independent suspension of all wheels and air axle suspension. All of the wheels are operated in dependence on turning trailer drawbar. Both of the axles are taken from front axle of bus SOR BN 12.

This thesis is focused on the front and rear suspension of the off-road buggy. For the front suspension is compared the concept with and without pushrod with respect to the kinematics parameters and the damping parameters. For the rear axle, there are three concepts that is compared, especially multilink suspension, double wishbone, and swing axle. Finally, structural design and dimensioning for front axle is performed.

La vérification à base de propriétés (PBV) est devenue un élément essentiel des flots de conception pour supporter la vérification de circuits complexes. Pour de tels composants où les techniques de vérification formelle ne peuvent s'appliquer, la vérification dynamique à base de propriétés connecte au circuit des moniteurs et des générateurs de test synthétisés à partir de propriétés pour construire de manière simple un environnement de test. Durant cette thèse une partie des travaux à consisté à développer une approche de synthèse de propriétés pour la génération de vecteurs de test. Dans ce contexte, les propriétés décrivent l'environnement du circuit sous test. Elles sont synthétisées en générateurs produisant des séquences de test respectant la propriété correspondante. Il est alors possible de spécifier et d'obtenir un modèle pour tout l'environnement du circuit. Alors que notre approche est modulaire, une méthode à base d'automates a été développée en collaboration avec l'université de McGill. La contribution la plus intéressante de cette thèse tiens dans la méthode qui a été mise en place pour synthétiser une spécification temporelle en un circuit correct par construction. Alors que les approches de l'état de l'art ont une complexité polynomiale, la nôtre est linéaire en la spécification. L'outil SyntHorus a été développé pour supporter cette méthode et synthétise en quelques secondes un circuit correct par construction à partir d'une spécification de plusieurs centaines de propriétés. La correction des générateurs et de la méthode de synthèse a été effectuée à l'aide du prouveur de théorème PVS. Les méthodes et outils développés durant cette thèse ont été validés, renforcés et transférés dans l'industrie grâce à plusieurs coopérations (Thalès Group, Dolphin Integration et ST-Microelectronics) et au projet ANR SFINCS.