Η μείωση της κατανάλωσης ισχύος αποτελεί το πιο σημαντικό πρόβλημα στα ψηφιακά ηλεκτρονικά κυκλώματα. Διάφορες μέθοδοι έχουν προταθεί, μεταξύ αυτών η χρήση επεξεργαστών δυναμικά μεταβαλλόμενου μήκους λέξης. Με αυτόν τον τρόπο, στους υπολογισμούς που απαιτείται μέγιστη ακρίβεια ο επεξεργαστής μπορεί να χρησιμοποιεί το μέγιστο δυνατό μήκος λέξης, ενώ σε αυτούς που η χαμηλή κατανάλωση ισχύος είναι ο κύριος στόχος μπορεί να χρησιμοποιεί μικρότερο μήκος λέξης. Τέτοιες απαιτήσεις συναντούνται συχνά σε εφαρμογές ψηφιακής επεξεργασίας σήματος, όπως για παράδειγμα στην κωδικοποίηση εικόνας. Για το λόγο αυτό μελετήθηκε ο αντίστροφος διακριτός μετασχηματισμός συνημιτόνου, ο οποίος αποτελεί το πιο ενεργοβόρο κομμάτι στην κωδικοποίηση εικόνας και η σχέση της ακρίβειάς του με το μήκος λέξης του επεξεργαστή. Στη συνέχεια κατασκευάστηκαν οι δομικές μονάδες για τις αριθμητικές πράξεις του επεξεργαστή, αθροιστές, αφαιρέτες και πολλαπλασιαστές με δύο διαφορετικά μήκη λέξης και τέλος οι υπόλοιπες μονάδες του. Τα αποτελέσματα της σύνθεσής του δείχνουν ότι απαιτεί περισσότερες πύλες για την κατασκευή του από έναν αντίστοιχο σταθερού μήκους, όμως προσφέρει πολλά πλεονεκτήματα στη μείωση της κατανάλωσης. / Power saving is today's most important problem in digital circuits. Several methods have been proposed, including the use of a dynamically changing processor wordlength. With the adoption of this technique, calculations requiring maximum accuracy would use the maximum processor wordlength, while in those where low power is the main target a smaller wordlength could be used. Such requirements are frequently found in digital signal processing applications, such as image coding. Consequently, this diploma thesis studies the inverse discrete cosine transform, which is the most power-intensive part in image coding and the relation of its accuracy to the processor wordlength. After that, the structure of the blocks of the arithmetic and logic unit is explained, in order for the adders, subtracters and multipliers to be constructed with two different wordlengths and finally the remaining units of the processor are designed. The synthesis results show that this processor requires more gates. On the other hand, it offers many advantages in static and dynamic power reduction.

Due to advances in digital computing much of the baseband signal processing of a communication system has moved into the digital domain from the analog domain. Within the domain of digital communication systems, Software Defined Radios (SDRs) allow for majority of the signal processing tasks to be implemented in reconfigurable digital hardware. However this comes at a cost of higher power and resource requirements. Therefore, highly efficient custom hardware implementations for SDRs are needed to make SDRs feasible for practical use. Efficient custom hardware motivates the use of fixed point arithmetic in the implementation of Digital Signal Processing (DSP) algorithms. This conversion to finite precision arithmetic introduces quantization noise in the system, which significantly affects the performance metrics of the system. As a result, characterizing quantization noise and its effects within a DSP system is an important challenge that needs to be addressed. Current models to do so significantly over-estimate the quantization effects, resulting in an over-allocation of hardware resources to implement a system. Polynomial Chaos Expansion (PCE) is a method that is currently gaining attention in modelling uncertainty in engineering systems. Although it has been used to analyze quantization effects in DSP systems, previous investigations have been limited to simple examples. The purpose of this thesis is to therefore introduce new techniques that allow the application of PCE to be scaled up to larger DSP blocks with many noise sources. Additionally, the thesis introduces design space exploration algorithms that leverage the accuracy of PCE simulations to estimate bitwidths for fixed point implementations of DSP systems. The advantages of using PCE over current modelling techniques will be presented though its application to case studies relevant to practice. These case studies include Sine Generators, Infinite Impulse Response (IIR) filters, Finite Impulse Response (FIR) filters, FM demodulators and Phase Locked Loops (PLLs). / Thesis / Master of Applied Science (MASc)

Sistemas de levitação magnética são inerentemente não-lineares e, quando con- trolados digitalmente, normalmente, esbarram em limitações do hardware empregado. O objetivo desta tese é apresentar aspectos teóricos e práticos durante a aplicação da teoria de controle H1 não-linear em sistemas de levitação magnética. A primeira con- tribuição desta tese é apresentar um procedimento de projeto de um controlador H1 não-linear que utiliza funções de ponderação com dinâmica, obtidas a partir do projeto de um controlador H1 linear. Assim como no caso linear, essas funções de ponderação possibilitam a rejeição de perturbações, ruídos de sensor, aumento da robustez, den- tre outras especificações. A segunda contribuição é apresentar um procedimento de conversão de uma rotina implementada em ponto-flutuante para ponto-fixo, utilizando minimização de norma l1, que foi implementada em um DSP de 32 bits em ponto- fixo. Resultados experimentais também são apresentados, nos quais a performance do controlador não-linear é especificamente avaliada na fase inicial de levitação. / Electromagnetic suspension systems are inherently nonlinear and often face hard- ware limitation when digitally controlled. The goal of this thesis is to present theoretical and practical aspects during the nonlinear H1 control applied on an electromagnetic suspension system. The first contribution is the design of a nonlinear H1 controller, including dynamic weighting functions, obtained from a linear H1 controller. Just as in the linear case, this dynamic weighting functions provide the disturbance and noise sensor rejection, robustness improvement, among other specifications. The second con- tribution is to present a procedure able to translate a floating-point algorithm into a fixed-point algorithm by using l1 norm minimization due to conversion error, which was then implemented into a 32-bit fixed-point DSP. Experimental results are also pre-sented, in which the performance of the nonlinear controller is evaluated specifically in the initial suspension phase.

L'accélération matérielle désigne l'utilisation d'architectures spécialisées pour effectuer certaines tâches plus vite ou plus efficacement que sur du matériel générique. Les accélérateurs ont traditionnellement été utilisés dans des environnements contraints en ressources, comme les systèmes embarqués. Cependant, avec la fin des règles empiriques ayant régi la conception de matériel pendant des décennies, ces quinze dernières années ont vu leur apparition dans les centres de calcul et des environnements de calcul haute performance. Les FPGAs constituent une plateforme d'implémentation commode pour de tels accélérateurs, autorisant des compromis subtils entre débit/latence, surface, énergie, précision, etc. Cependant, identifier de bons compromis représente un défi, dans la mesure où l'espace de recherche est généralement très large. Cette thèse propose des techniques de conception pour résoudre ce problème. Premièrement, nous nous intéressons aux compromis entre performance et précision pour la conversion flottant vers fixe. L'utilisation de l'arithmétique en virgule fixe au lieu de l'arithmétique flottante est un moyen efficace de réduire l'utilisation de ressources matérielles, mais affecte la précision des résultats. La validité d'une implémentation en virgule fixe peut être évaluée avec des simulations, ou en dérivant des modèles de précision analytiques de l'algorithme traité. Comparées aux approches simulatoires, les méthodes analytiques permettent une exploration plus exhaustive de l'espace de recherche, autorisant ainsi l'identification de solutions potentiellement meilleures. Malheureusement, elles ne sont applicables qu'à un jeu limité d'algorithmes. Dans la première moitié de cette thèse, nous étendons ces techniques à des filtres linéaires multi-dimensionnels, comme des algorithmes de traitement d'image. Notre méthode est implémentée comme une analyse statique basée sur des techniques de compilation polyédrique. Elle est validée en la comparant à des simulations sur des données réelles. Dans la seconde partie de cette thèse, on se concentre sur les stencils itératifs. Les stencils forment un motif de calcul émergeant naturellement dans de nombreux algorithmes utilisés en calcul scientifique ou dans l'embarqué. À cause de cette diversité, il n'existe pas de meilleure architecture pour les stencils de façon générale : chaque algorithme possède des caractéristiques uniques (intensité des calculs, nombre de dépendances) et chaque application possède des contraintes de performance spécifiques. Pour surmonter ces difficultés, nous proposons une famille d'architectures pour stencils. Nous offrons des paramètres de conception soigneusement choisis ainsi que des modèles analytiques simples pour guider l'exploration. Notre architecture est implémentée sous la forme d'un flot de génération de code HLS, et ses performances sont mesurées sur la carte. Comme les résultats le démontrent, nos modèles permettent d'identifier les solutions les plus intéressantes pour chaque cas d'utilisation. / Hardware acceleration is the use of custom hardware architectures to perform some computations faster or more efficiently than on general-purpose hardware. Accelerators have traditionally been used mostly in resource-constrained environments, such as embedded systems, where resource-efficiency was paramount. Over the last fifteen years, with the end of empirical scaling laws, they also made their way to datacenters and High-Performance Computing environments. FPGAs constitute a convenient implementation platform for such accelerators, allowing subtle, application-specific trade-offs between all performance metrics (throughput/latency, area, energy, accuracy, etc.) However, identifying good trade-offs is a challenging task, as the design space is usually extremely large. This thesis proposes design methodologies to address this problem. First, we focus on performance-accuracy trade-offs in the context of floating-point to fixed-point conversion. Usage of fixed-point arithmetic instead of floating-point is an affective way to reduce hardware resource usage, but comes at a price in numerical accuracy. The validity of a fixed-point implementation can be assessed using either numerical simulations, or with analytical models derived from the algorithm. Compared to simulation-based methods, analytical approaches enable more exhaustive design space exploration and can thus increase the quality of the final architecture. However, their are currently only applicable to limited sets of algorithms. In the first part of this thesis, we extend such techniques to multi-dimensional linear filters, such as image processing kernels. Our technique is implemented as a source-level analysis using techniques from the polyhedral compilation toolset, and validated against simulations with real-world input. In the second part of this thesis, we focus on iterative stencil computations, a naturally-arising pattern found in many scientific and embedded applications. Because of this diversity, there is no single best architecture for stencils: each algorithm has unique computational features (update formula, dependences) and each application has different performance constraints/requirements. To address this problem, we propose a family of hardware accelerators for stencils, featuring carefully-chosen design knobs, along with simple performance models to drive the exploration. Our architecture is implemented as an HLS-optimized code generation flow, and performance is measured with actual execution on the board. We show that these models can be used to identify the most interesting design points for each use case.

Sistemas de levitação magnética são inerentemente não-lineares e, quando con- trolados digitalmente, normalmente, esbarram em limitações do hardware empregado. O objetivo desta tese é apresentar aspectos teóricos e práticos durante a aplicação da teoria de controle H1 não-linear em sistemas de levitação magnética. A primeira con- tribuição desta tese é apresentar um procedimento de projeto de um controlador H1 não-linear que utiliza funções de ponderação com dinâmica, obtidas a partir do projeto de um controlador H1 linear. Assim como no caso linear, essas funções de ponderação possibilitam a rejeição de perturbações, ruídos de sensor, aumento da robustez, den- tre outras especificações. A segunda contribuição é apresentar um procedimento de conversão de uma rotina implementada em ponto-flutuante para ponto-fixo, utilizando minimização de norma l1, que foi implementada em um DSP de 32 bits em ponto- fixo. Resultados experimentais também são apresentados, nos quais a performance do controlador não-linear é especificamente avaliada na fase inicial de levitação. / Electromagnetic suspension systems are inherently nonlinear and often face hard- ware limitation when digitally controlled. The goal of this thesis is to present theoretical and practical aspects during the nonlinear H1 control applied on an electromagnetic suspension system. The first contribution is the design of a nonlinear H1 controller, including dynamic weighting functions, obtained from a linear H1 controller. Just as in the linear case, this dynamic weighting functions provide the disturbance and noise sensor rejection, robustness improvement, among other specifications. The second con- tribution is to present a procedure able to translate a floating-point algorithm into a fixed-point algorithm by using l1 norm minimization due to conversion error, which was then implemented into a 32-bit fixed-point DSP. Experimental results are also pre-sented, in which the performance of the nonlinear controller is evaluated specifically in the initial suspension phase.

Compilers, complex programs with the potential to greatly facilitate software and hardware design. This thesis focuses on enhancing the Spade hardware description language, known for its user-friendly approach to hardware design. In the realm of hardware development data size - for numerical values data size is known as "wordlength" - plays a critical role for reducing the hardware resources. This study presents an innovative approach that seamlessly integrates wordlength inference directly into the Spade language, enabling the over-estimation of numeric data sizes solely from the program's source code. The methodology involves iterative development, incorporating various smaller implementations and evaluations, reminiscent of an agile approach. To assess the efficacy of the wordlength inference, multiple place and route operations are performed on identical Spade code using various versions of nextpnr. Surprisingly, no discernible impact on hardware resource utilization emerges from the modifications introduced in this thesis. Nonetheless, the true significance of this endeavor lies in its potential to unlock more advanced language features within the Spade compiler. It is important to note that while the wordlength inference proposed in this thesis shows promise, it necessitates further integration efforts to realize its full potential.