• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 3
  • 1
  • 1
  • 1
  • Tagged with
  • 7
  • 7
  • 3
  • 3
  • 2
  • 2
  • 2
  • 2
  • 2
  • 2
  • 2
  • 2
  • 2
  • 2
  • 2
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Optimering baserad på vinds tillgångar / Yield Optimization based on wind resource

Neto, João Borges Coutinho Amaral January 2010 (has links)
In one of the largest renewable energy sectors, the Wind, research on maintenance on windturbines is surprisingly nearly nonexistent. No meaningful work has been made on optimizingthe scheduled maintenance process. Filling this gap this thesis stems.Unplanned maintenance is commonly synonym to large energy loss since the wind turbine mustbe stopped nearly throughout the whole duration of the maintenance procedure. All partiesevolved in the sector are hindered by this fact. It is therefore not only in all the sectors’ playersbut also the general publics’ interest to optimize this process for a more sustainable world.Responsible for all the calculations is a model, which was fully developed for this thesis and ispart of it. Having considered several programming languages the choice was Excel (VBA); beingthis software spread worldwide it encourages the models’ global implementation. Easy to use,versatility and accurate and prompt results were the guidelines for its developments. A weatherforecast is the fundamental input.Running the model on two different wind farms gave conclusive results. The energy loss wasreduced up to 71%. Also in some cases the time frame was cut up to 62%.Even with these promising figures energy loss must be significant in order to have a realeconomical impact. Nevertheless the model unveils the most convenient schedule formaintenance and its implementation is exclusively beneficial.
2

Novel MEMS Tunable Capacitors with Linear Capacitance-Voltage Response Considering Fabrication Uncertainties

Shavezipur, Mohammad January 2008 (has links)
Electrostatically actuated parallel-plate MEMS tunable capacitors are desired elements for different applications including sensing, actuating and communications and RF (radio frequency) engineering for their superior characteristics such as quick response, high Q-factor and small size. However, due to the nature of their coupled electrostatic-structural physics, they suffer from low tuning range of 50% and have nonlinear capacitance-voltage (C-V) responses which are very sensitive to the voltage change near pull-in voltage. Numerous studies in the literature introduce new designs with high tunability ranging from 100% to over 1500%, but improvement of the nonlinearity and high sensitivity of the capacitor response have not received enough attention. In this thesis, novel highly tunable capacitors with high linearity are proposed to reduce sensitivity to the voltage changes near pull-in. The characteristic equations of a perfectly linear capacitor are first derived for two- and three-plate capacitors to obtain insight for developing linear capacitance-voltage responses. The devices proposed in this research may be classified into three categories: designs with nonlinear structural rigidities, geometric modifications and flexible moving electrodes. The concept of nonlinear supporting beams is exploited to develop parallel-plate capacitors with partially linear C-V curves. Novel electrodes with triangular, trapezoidal, butterfly, zigzag and fishbone shapes and structural/geometric nonlinearities are used to increase the linearity and tuning ratio of the response. To investigate the capacitors' behavior, an analytical approximate model is developed which can drastically decrease the computation time. The model is ideal for early design and optimization stages. Using this model, design variables are optimized for maximum linearity of the C-V responses. The results of the proposed modeling approach are verified by ANSYS FEM simulations and/or experimental data. When the fabrication process has dimensional limitations, design modifications and geometric enhancements are implemented to improve the linearity of the C-V response. The design techniques proposed in this thesis can provide tunabilities ranging from 80% to over 350% with highly linear regions in resulting C-V curves. Due to the low sensitivity of the capacitance to voltage changes in new designs, the entire tuning range is usable. Furthermore, the effect of fabrication uncertainties on parallel-plate capacitors performance is studied and a sensitivity analysis is performed to find the design variables with maximum impact on the C-V curves. An optimization method is then introduced to immunize the design against fabrication uncertainties and to maximize the production yield for MEMS tunable capacitors. The method approximates the feasible region and the probability distribution functions of the design variables to directly maximize the yield. Numerical examples with two different sets of design variables demonstrate significant increase in the yield. The presented optimization method can be advantageously utilized in design stage to improve the yield without increasing the fabrication cost or complexity.
3

Novel MEMS Tunable Capacitors with Linear Capacitance-Voltage Response Considering Fabrication Uncertainties

Shavezipur, Mohammad January 2008 (has links)
Electrostatically actuated parallel-plate MEMS tunable capacitors are desired elements for different applications including sensing, actuating and communications and RF (radio frequency) engineering for their superior characteristics such as quick response, high Q-factor and small size. However, due to the nature of their coupled electrostatic-structural physics, they suffer from low tuning range of 50% and have nonlinear capacitance-voltage (C-V) responses which are very sensitive to the voltage change near pull-in voltage. Numerous studies in the literature introduce new designs with high tunability ranging from 100% to over 1500%, but improvement of the nonlinearity and high sensitivity of the capacitor response have not received enough attention. In this thesis, novel highly tunable capacitors with high linearity are proposed to reduce sensitivity to the voltage changes near pull-in. The characteristic equations of a perfectly linear capacitor are first derived for two- and three-plate capacitors to obtain insight for developing linear capacitance-voltage responses. The devices proposed in this research may be classified into three categories: designs with nonlinear structural rigidities, geometric modifications and flexible moving electrodes. The concept of nonlinear supporting beams is exploited to develop parallel-plate capacitors with partially linear C-V curves. Novel electrodes with triangular, trapezoidal, butterfly, zigzag and fishbone shapes and structural/geometric nonlinearities are used to increase the linearity and tuning ratio of the response. To investigate the capacitors' behavior, an analytical approximate model is developed which can drastically decrease the computation time. The model is ideal for early design and optimization stages. Using this model, design variables are optimized for maximum linearity of the C-V responses. The results of the proposed modeling approach are verified by ANSYS FEM simulations and/or experimental data. When the fabrication process has dimensional limitations, design modifications and geometric enhancements are implemented to improve the linearity of the C-V response. The design techniques proposed in this thesis can provide tunabilities ranging from 80% to over 350% with highly linear regions in resulting C-V curves. Due to the low sensitivity of the capacitance to voltage changes in new designs, the entire tuning range is usable. Furthermore, the effect of fabrication uncertainties on parallel-plate capacitors performance is studied and a sensitivity analysis is performed to find the design variables with maximum impact on the C-V curves. An optimization method is then introduced to immunize the design against fabrication uncertainties and to maximize the production yield for MEMS tunable capacitors. The method approximates the feasible region and the probability distribution functions of the design variables to directly maximize the yield. Numerical examples with two different sets of design variables demonstrate significant increase in the yield. The presented optimization method can be advantageously utilized in design stage to improve the yield without increasing the fabrication cost or complexity.
4

Amélioration des connaissances de la physiologie de Candida shehatae pour une quantification des phénomènes biologiques et leur modélisation lors de la fermentation alcoolique des pentoses / Improvement of knowledge about Candida shehatae physiology to quantified biological phenomenon and model them during alcoholic fermentation of pentose

Montheard, Julie 26 September 2013 (has links)
Résumé confidentiel / No abstract
5

Design and Optimization of Microwave Circuits and Systems Using Artificial Intelligence Techniques

Pratap, Rana Jitendra 19 July 2005 (has links)
In this thesis, a new approach combining neural networks and genetic algorithms is presented for microwave design. In this method, an accurate neural network model is developed from the experimental data. This neural network model is used to perform sensitivity analysis and derive response surfaces. An innovative technique is then applied in which genetic algorithms are coupled with the neural network model to assist in synthesis and optimization. The proposed method is used for modeling and analysis of circuit parameters for flip chip interconnects up to 35 GHz, as well as for design of multilayer inductors and capacitors at 1.9 GHz and 2.4 GHz. The method was also used to synthesize mm wave low pass filters in the range of 40-60 GHz. The devices obtained from layout parameters predicted by the neuro-genetic design method yielded electrical response close to the desired value (95% accuracy). The proposed method also implements a weighted priority scheme to account for tradeoffs in microwave design. This scheme was implemented to synthesize bandpass filters for 802.11a and HIPERLAN wireless LAN applications in the range of 5-6 GHz. This research also develops a novel neuro-genetic design centering methodology for yield enhancement and design for manufacturability of microwave devices and circuits. A neural network model is used to calculate yield using Monte Carlo methods. A genetic algorithm is then used for yield optimization. The proposed method has been used for yield enhancement of SiGe heterojunction bipolar transistor and mm wave voltage-controlled oscillator. It results in significant yield enhancement of the SiGe HBTs (from 25 % to 75 %) and VCOs (from 8 % to 85 %). The proposed method is can be extended for device, circuit, package, and system level integrated co-design since it can handle a large number of design variables without any assumptions about the component behavior. The proposed algorithm could be used by microwave community for design and optimization of microwave circuits and systems with greater accuracy while consuming less computational time.
6

Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits

Mukherjee, Souvik 02 July 2007 (has links)
The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.
7

ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS

AGARWAL, ANURADHA January 2005 (has links)
No description available.

Page generated in 0.0928 seconds