The thesis “Acceptance and use of the Service Oriented Computing paradigm: the IT professionals’ perspective” focuses on the question: what are the critical factors that influence IT professionals’ intentions to accept and use the Service Oriented Computing (SOC) approach to systems development? This work considers IT professionals as the key stakeholders in the SOC acceptance and use process and argues that the acceptance and practical use of SOC depends – at an early acceptance stage – primarily on the individual-level acceptance decisions made by senior IT professionals working for an organisation. Consequently, SOC acceptance and use (in its early stage) is seen as a bottom-up process driven, and to a high degree controlled, by the “early adopters” (Rogers 1995) of this technological paradigm (i.e. involved senior IT professionals). Although SOC is considered the enabling technological approach in many different future areas (e.g. eBusiness, eGovernment, eScience etc.), very little research exists on the process of practical acceptance of this paradigm, in particular focusing on the perspective of the “early stage” key stakeholders of this acceptance process, namely the IT professionals. This thesis consists of four major parts. First, it reviews existing literature on technology acceptance and use and confirms the absence of an established theoretical framework in the domain of individual-level technology acceptance in the IT industry. Second, based on data collected in a series of exploratory interviews with senior IT practitioners, an initial model explaining the acceptance and use of SOC among IT professionals is being proposed. Third, the derived model is revised and reformulated using an eGovernment case study. And forth, based on the refined model, a survey instrument is developed, pilot-tested and administered to senior IT professionals currently using the SOC approach to systems development in their professional work. This thesis makes a contribution to IS research in several ways. While there exists extensive, well-grounded and well-accepted research in the domain of “IT end-user” individual-level technology acceptance, the research on technology acceptance in the IT industry (i.e. technology acceptance by the IT professionals) is very limited, and nearly all studies carried out in this IS research field are concerned with established approaches or technologies. The current study is among the few examining the perspective of “early adopters” or “innovators” (Rogers 1995) instead of investigating the acceptance process of “early majority” or even “late majority”. Moreover, to the author’s knowledge it is the first study examining the process of individual-level SOC acceptance with a particular focus on the perspective of the “early stage” key stakeholders of this acceptance process, namely the IT professionals. One of the additional strengths of the study is the usage of multiple research methodologies – exploratory open-ended interviews, qualitative case study and web-based survey. This research is expected to be very interesting to researchers focusing on technology acceptance in general and on technology acceptance in the IT industry in particular. This research might also be of interest to IT practitioners considering to accept and use the SOC approach in their future applications.

Research Doctorate - Doctor of Philosophy (PhD) / Amidst growing concerns about global warming, efforts to reduce atmospheric CO2 concentrations (i.e. C sequestration) have received widespread attention. One approach to C sequestration is to increase the amount of C stored in terrestrial ecosystems, through improved land management. Terrestrial ecosystems represent a critical element of the C interchange system, however a lack of understanding of the C cycle at regional and sub-regional scales means that they represent a source of primary uncertainty in the overall C budget. This thesis aims to address this deficiency by developing an understanding of catchment-scale processes critical for accurate quantification of C in the landscape. An investigation into the spatial and temporal dynamics of soil organic carbon (SOC) was conducted for a 150ha temperate grassland catchment in the Upper Hunter Valley, New South Wales, Australia. The major factors controlling the movement, storage, and loss of SOC were investigated, including climate, vegetation cover, soil redistribution processes, topography, land use, and soil type. This study falls into four broad areas. In the first part of this study the spatio-temporal dynamics of soil moisture and temperature at the catchment scale are assessed for a range of soil depths. Data recorded from a network of monitoring sites located throughout the study catchment was compared with independently derived soil moisture and temperature data sets. The data indicates that soil moisture and temperature in surface soil layers were highly dynamic, in their response to rainfall and incoming solar radiation, respectively. Deeper soil layers however were less dynamic, with longer lag times observed with increasing soil depth, as topography, soil type, and landscape position were the dominant controlling factors. Climate related variables are important factors affecting plant growth and net primary productivity. The second part of the study quantified spatial and temporal vegetation patterns using both field-based measurements of above-ground biomass and remotely sensed vegetation indices from the MODIS and Landsat TM 5 platforms. A strong and statistically significant relationship was found between climate variables and MODIS derived NDVI, leading to the development of a predictive vegetation cover model using ground-based soil moisture, soil temperature, and sunshine hours data. The ability of remotely sensed data to capture vegetation spatial patterns was found to be limited, while it was found to be a good predictor of temporal above-ground biomass trends, enabling net primary productivity to be quantified over the three-year study period. In the third part of the thesis soil redistribution patterns and erosion rates were quantified using the caesium-137 method and empirical and physically-based modelling approaches. The impact of soil redistribution processes on SOC distribution was investigated, and the amount of erosion derived SOC loss quantified. A significant proportion of SOC stored within the catchment was found below a soil depth of 0.30m, which is the depth of sampling set out in the IPCC and Australian Greenhouse Office guidelines for carbon accounting. Soil depth was identified as a key factor controlling the spatial distribution of SOC, which is in turn determined by position in the landscape (i.e. topography). The fourth and final part of the study describes how data on erosion derived SOC loss were used in conjunction with net primary productivity estimates, to establish a SOC balance. This involved mapping the spatial distribution of SOC using a high resolution digital elevation model of the catchment, in conjunction with soil depth measurements, and quantifying the total SOC store of the catchment. It was observed that temporal changes in SOC were minimal over the limited three-year study period, however, the continuity of catchment management practices over the previous decades suggest that steady-state conditions have perhaps been reached. The study concludes that the key to increasing the amount of SOC and enhancing carbon sequestration in the soil, is to increase the amount of SOC stored at depth within the soil profile, where factors such as soil moisture and temperature, which control decomposition rates, are less dynamic in space and time, and where SOC concentrations will be less vulnerable to changes occurring at the surface in response to global warming and climate change.

Security Monitoring Platform (SMP) represents multiple detective controls applied inthe enterprise to protect against cyberattacks. Building SMP is a challenging task, as itconsists of multiple systems that require integration. This paper introduces a framework thatcompiles various aspects of Security Monitoring and presents respective requirements sets.SMP framework provides guidance for establishing a risk-based detection platform,augmented with automation, threat intelligence and analytics capabilities. It provides morebroad view on the problem of Security Monitoring in the enterprise context and can assist inthe platform creation. The proposed solution has been built using Design Science ResearchMethodology and contains of twenty requirements for building SMP. Expert evaluation andcomparison with similar frameworks show potential value in holistic approach to the problem,as well as indicate the need for further research.

O projeto de sistemas eletrônicos atuais segue o paradigma do reuso de componentes de hardware. Este paradigma reduz a complexidade do projeto de um chip, mas cria novos desafios para o projetista do sistema em relação ao teste do produto final. O acesso aos núcleos profundamente embutidos no sistema, a integração dos diversos métodos de teste e a otimização dos diversos fatores de custo do sistema são alguns dos problemas que precisam ser resolvidos durante o planejamento do teste de produção do novo circuito. Neste contexto, esta tese propõe duas abordagens para o planejamento de teste de sistemas integrados. As abordagens propostas têm como principal objetivo a redução dos custos de teste através do reuso dos recursos de hardware disponíveis no sistema e da integração do planejamento de teste no fluxo de projeto do circuito. A primeira abordagem considera os sistemas cujos componentes se comunicam através de conexões dedicadas ou barramentos funcionais. O método proposto consiste na definição de um mecanismo de acesso aos componentes do circuito e de um algoritmo para exploração do espaço de projeto. O mecanismo de acesso prevê o reuso das conexões funcionais, o uso de barramentos de teste locais, núcleos transparentes e outros modos de passagem do sinal de teste. O algoritmo de escalonamento de teste é definido juntamente com o mecanismo de acesso, de forma que diferentes combinações de custos sejam exploradas. Além disso, restrições de consumo de potência do sistema podem ser consideradas durante o escalonamento dos testes. Os resultados experimentais apresentados para este método mostram claramente a variedade de soluções que podem ser exploradas e a efi- ciência desta abordagem na otimização do teste de um sistema complexo. A segunda abordagem de planejamento de teste propõe o reuso de redes em-chip como mecanismo de acesso aos componentes dos sistemas construídos sobre esta plataforma de comunicação. Um algoritmo de escalonamento de teste que considera as restrições de potência da aplicação é apresentado e a estratégia de teste é avaliada para diferentes configurações do sistema. Os resultados experimentais mostram que a capacidade de paralelização da rede em-chip pode ser explorada para reduzir o tempo de teste do sistema, enquanto os custos de área e pinos de teste são drasticamente minimizados. Neste manuscrito, os principais problemas relacionados ao teste dos sistemas integrados baseados em componentes virtuais são identificados e as soluções já apresentadas na literatura são discutidas. Em seguida, os problemas tratados por este traballho são listados e as abordagens propostas são detalhadas. Ambas as técnicas são validadas através dos sistemas disponíveis no ITC’02 SoC Test Benchmarks. As técnicas propostas são ainda comparadas com outras abordagens de teste apresentadas recentemente. Esta comparação confirma a eficácia dos métodos desenvolvidos nesta tese. / Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.

Esta dissertação propõe um projeto de aerogerador que é composto de uma turbina eólica de cinco pás, acoplada a um difusor e um gerador elétrico, com a finalidade de gerar energia elétrica com ventos de velocidade a partir de 4 m/s. São apresentados os pressupostos teóricos referentes ao estudo e dimensionamento aerodinâmico de uma pá, baseados principalmente na teoria do disco atuador e na teoria aerodinâmica, através do método de Betz. É feito o estudo de um difusor para ser acoplado à turbina com o objetivo de aumentar o aproveitamento energético. No final foram estudadas as principais topologias utilizadas para a geração eólica e é selecionado o gerador síncrono de ímãs permanentes. A seguir foram estudadas e dimensionadas as partes ativas do gerador (diretamente envolvidas na conversão eletromagnética). É projetado um aerogerador trifásico com enrolamentos distribuídos. O rotor, que é acoplado às pás, localiza-se internamente. Os ímãs permanentes de Neodímio-Boro-Ferro são montados na superfície do rotor. Conclui-se com a avaliação do aerogerador proposto com base nas simulações computacionais de seu desempenho. / This thesis proposes a wind generator design which combines a five blade wind turbine that is attached to a diffuser and an electrical generator. The design aims to produce electric power from 4 m/s starting wind speeds. It presents the theoretical study concerning the design and aerodynamics of a blade, commonly based on the theory of actuator disc and aerodynamic theory, through the method of Betz. A study was conducted on a diffuser to be coupled to the turbine in order to increase the energy utilization. In the end, the main topologies used for wind generation were presented, and the permanent magnet synchronous generator was selected. Next, all the active parts of the generator (directly involved in electromagnetic conversion) were studied and determined. An outer stator with three-phase distributed windings was designed. The rotor, which is coupled to the blades, is located internally. The Neodymium-Iron-Boron permanent magnets are mounted on the rotor surface. It is concluded with an evaluation of the proposed wind generator in accordance with its behavior computational simulations.

O projeto de sistemas eletrônicos atuais segue o paradigma do reuso de componentes de hardware. Este paradigma reduz a complexidade do projeto de um chip, mas cria novos desafios para o projetista do sistema em relação ao teste do produto final. O acesso aos núcleos profundamente embutidos no sistema, a integração dos diversos métodos de teste e a otimização dos diversos fatores de custo do sistema são alguns dos problemas que precisam ser resolvidos durante o planejamento do teste de produção do novo circuito. Neste contexto, esta tese propõe duas abordagens para o planejamento de teste de sistemas integrados. As abordagens propostas têm como principal objetivo a redução dos custos de teste através do reuso dos recursos de hardware disponíveis no sistema e da integração do planejamento de teste no fluxo de projeto do circuito. A primeira abordagem considera os sistemas cujos componentes se comunicam através de conexões dedicadas ou barramentos funcionais. O método proposto consiste na definição de um mecanismo de acesso aos componentes do circuito e de um algoritmo para exploração do espaço de projeto. O mecanismo de acesso prevê o reuso das conexões funcionais, o uso de barramentos de teste locais, núcleos transparentes e outros modos de passagem do sinal de teste. O algoritmo de escalonamento de teste é definido juntamente com o mecanismo de acesso, de forma que diferentes combinações de custos sejam exploradas. Além disso, restrições de consumo de potência do sistema podem ser consideradas durante o escalonamento dos testes. Os resultados experimentais apresentados para este método mostram claramente a variedade de soluções que podem ser exploradas e a efi- ciência desta abordagem na otimização do teste de um sistema complexo. A segunda abordagem de planejamento de teste propõe o reuso de redes em-chip como mecanismo de acesso aos componentes dos sistemas construídos sobre esta plataforma de comunicação. Um algoritmo de escalonamento de teste que considera as restrições de potência da aplicação é apresentado e a estratégia de teste é avaliada para diferentes configurações do sistema. Os resultados experimentais mostram que a capacidade de paralelização da rede em-chip pode ser explorada para reduzir o tempo de teste do sistema, enquanto os custos de área e pinos de teste são drasticamente minimizados. Neste manuscrito, os principais problemas relacionados ao teste dos sistemas integrados baseados em componentes virtuais são identificados e as soluções já apresentadas na literatura são discutidas. Em seguida, os problemas tratados por este traballho são listados e as abordagens propostas são detalhadas. Ambas as técnicas são validadas através dos sistemas disponíveis no ITC’02 SoC Test Benchmarks. As técnicas propostas são ainda comparadas com outras abordagens de teste apresentadas recentemente. Esta comparação confirma a eficácia dos métodos desenvolvidos nesta tese. / Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.

Esta dissertação propõe um projeto de aerogerador que é composto de uma turbina eólica de cinco pás, acoplada a um difusor e um gerador elétrico, com a finalidade de gerar energia elétrica com ventos de velocidade a partir de 4 m/s. São apresentados os pressupostos teóricos referentes ao estudo e dimensionamento aerodinâmico de uma pá, baseados principalmente na teoria do disco atuador e na teoria aerodinâmica, através do método de Betz. É feito o estudo de um difusor para ser acoplado à turbina com o objetivo de aumentar o aproveitamento energético. No final foram estudadas as principais topologias utilizadas para a geração eólica e é selecionado o gerador síncrono de ímãs permanentes. A seguir foram estudadas e dimensionadas as partes ativas do gerador (diretamente envolvidas na conversão eletromagnética). É projetado um aerogerador trifásico com enrolamentos distribuídos. O rotor, que é acoplado às pás, localiza-se internamente. Os ímãs permanentes de Neodímio-Boro-Ferro são montados na superfície do rotor. Conclui-se com a avaliação do aerogerador proposto com base nas simulações computacionais de seu desempenho. / This thesis proposes a wind generator design which combines a five blade wind turbine that is attached to a diffuser and an electrical generator. The design aims to produce electric power from 4 m/s starting wind speeds. It presents the theoretical study concerning the design and aerodynamics of a blade, commonly based on the theory of actuator disc and aerodynamic theory, through the method of Betz. A study was conducted on a diffuser to be coupled to the turbine in order to increase the energy utilization. In the end, the main topologies used for wind generation were presented, and the permanent magnet synchronous generator was selected. Next, all the active parts of the generator (directly involved in electromagnetic conversion) were studied and determined. An outer stator with three-phase distributed windings was designed. The rotor, which is coupled to the blades, is located internally. The Neodymium-Iron-Boron permanent magnets are mounted on the rotor surface. It is concluded with an evaluation of the proposed wind generator in accordance with its behavior computational simulations.

Esta dissertação propõe um projeto de aerogerador que é composto de uma turbina eólica de cinco pás, acoplada a um difusor e um gerador elétrico, com a finalidade de gerar energia elétrica com ventos de velocidade a partir de 4 m/s. São apresentados os pressupostos teóricos referentes ao estudo e dimensionamento aerodinâmico de uma pá, baseados principalmente na teoria do disco atuador e na teoria aerodinâmica, através do método de Betz. É feito o estudo de um difusor para ser acoplado à turbina com o objetivo de aumentar o aproveitamento energético. No final foram estudadas as principais topologias utilizadas para a geração eólica e é selecionado o gerador síncrono de ímãs permanentes. A seguir foram estudadas e dimensionadas as partes ativas do gerador (diretamente envolvidas na conversão eletromagnética). É projetado um aerogerador trifásico com enrolamentos distribuídos. O rotor, que é acoplado às pás, localiza-se internamente. Os ímãs permanentes de Neodímio-Boro-Ferro são montados na superfície do rotor. Conclui-se com a avaliação do aerogerador proposto com base nas simulações computacionais de seu desempenho. / This thesis proposes a wind generator design which combines a five blade wind turbine that is attached to a diffuser and an electrical generator. The design aims to produce electric power from 4 m/s starting wind speeds. It presents the theoretical study concerning the design and aerodynamics of a blade, commonly based on the theory of actuator disc and aerodynamic theory, through the method of Betz. A study was conducted on a diffuser to be coupled to the turbine in order to increase the energy utilization. In the end, the main topologies used for wind generation were presented, and the permanent magnet synchronous generator was selected. Next, all the active parts of the generator (directly involved in electromagnetic conversion) were studied and determined. An outer stator with three-phase distributed windings was designed. The rotor, which is coupled to the blades, is located internally. The Neodymium-Iron-Boron permanent magnets are mounted on the rotor surface. It is concluded with an evaluation of the proposed wind generator in accordance with its behavior computational simulations.

O projeto de sistemas eletrônicos atuais segue o paradigma do reuso de componentes de hardware. Este paradigma reduz a complexidade do projeto de um chip, mas cria novos desafios para o projetista do sistema em relação ao teste do produto final. O acesso aos núcleos profundamente embutidos no sistema, a integração dos diversos métodos de teste e a otimização dos diversos fatores de custo do sistema são alguns dos problemas que precisam ser resolvidos durante o planejamento do teste de produção do novo circuito. Neste contexto, esta tese propõe duas abordagens para o planejamento de teste de sistemas integrados. As abordagens propostas têm como principal objetivo a redução dos custos de teste através do reuso dos recursos de hardware disponíveis no sistema e da integração do planejamento de teste no fluxo de projeto do circuito. A primeira abordagem considera os sistemas cujos componentes se comunicam através de conexões dedicadas ou barramentos funcionais. O método proposto consiste na definição de um mecanismo de acesso aos componentes do circuito e de um algoritmo para exploração do espaço de projeto. O mecanismo de acesso prevê o reuso das conexões funcionais, o uso de barramentos de teste locais, núcleos transparentes e outros modos de passagem do sinal de teste. O algoritmo de escalonamento de teste é definido juntamente com o mecanismo de acesso, de forma que diferentes combinações de custos sejam exploradas. Além disso, restrições de consumo de potência do sistema podem ser consideradas durante o escalonamento dos testes. Os resultados experimentais apresentados para este método mostram claramente a variedade de soluções que podem ser exploradas e a efi- ciência desta abordagem na otimização do teste de um sistema complexo. A segunda abordagem de planejamento de teste propõe o reuso de redes em-chip como mecanismo de acesso aos componentes dos sistemas construídos sobre esta plataforma de comunicação. Um algoritmo de escalonamento de teste que considera as restrições de potência da aplicação é apresentado e a estratégia de teste é avaliada para diferentes configurações do sistema. Os resultados experimentais mostram que a capacidade de paralelização da rede em-chip pode ser explorada para reduzir o tempo de teste do sistema, enquanto os custos de área e pinos de teste são drasticamente minimizados. Neste manuscrito, os principais problemas relacionados ao teste dos sistemas integrados baseados em componentes virtuais são identificados e as soluções já apresentadas na literatura são discutidas. Em seguida, os problemas tratados por este traballho são listados e as abordagens propostas são detalhadas. Ambas as técnicas são validadas através dos sistemas disponíveis no ITC’02 SoC Test Benchmarks. As técnicas propostas são ainda comparadas com outras abordagens de teste apresentadas recentemente. Esta comparação confirma a eficácia dos métodos desenvolvidos nesta tese. / Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.

The main objective of this study has been to explore how art therapists experience the visual art´s that can be used in the promotion of health among people with depression - and anxiety disorders. The concept of SOC- sense of coherence has been a central term and a link between imaging and SOC were identified in the study. The underlying method in the study was a qualitative form, where semi-structured interviews were used. Through a strategic- sample five female art therapist were contacted, who all came to participate in the study. The study is essentially based on hermeneutical method and the analysis of interview material has been analyst by using thematic analysis. The results indicate that the therapists experiences shows that  visual art can be a support for people with depression- and anxiety disorders. The SOC- concept made its mark in the result and it came to show that the visual art´s may be a support for people with depression- and anxiety disorders. Visual art can help people with depression- and anxiety disorders to get more understanding and tools to manage their state according to the therapists.