Les progrès des technologies de la micro-électronique ont permis d'embarquer des circuits numériques dans des objets multiples et divers (téléphones, GPS, automobiles, etc.) dont ils ont enrichi les fonctionnalités et amélioré les performances à moindre coût. Conjointement, l'essor rapide et constant de ces applications a amené des contraintes de conception sans précédent (contraintes de coût, de performance, de consommation, etc.). Dans ce contexte, l'émergence des architectures reconfigurables à grain épais a ouvert la voie à de nouveaux compromis entre performances et flexibilité. À ce jour, la mise en oeuvre des mécanismes de reconfiguration matérielle a principalement concerné les aspects calculatoires de ces architectures. Or, les applications embarquées (multimédia) manipulent des volumes de données croissants, engendrant une sollicitation intensive des ressources de mémorisation. En outre, l'hétérogénéité et l'évolutivité des traitements induits ne permet plus d'envisager l'élaboration de solutions de stockage dédiées dans un objectif de performance et de maîtrise de la consommation. Aussi, dans le cadre de cette thèse, nous avons développé le modèle RTL, valide et fonctionnel, d'une architecture reconfigurable que nous avons nommé MOREA (acronyme de Memory-Oriented Reconfigurable Embedded Architecture) et dont la structure mémoire est flexible. Celle-ci est organisée en un pavage de tuiles de traitement et de stockage qui supportent les processus d'une application. Au sein d'une tuile, les tâches du processus sont exécutées par quatre clusters qui intègrent des ressources mémoire et de calcul. Ces clusters communiquent entre eux et avec une mémoire de tuile, contenant les données partagées par les tâches du processus, grâce à une interconnexion flexible de type crossbar. Dès lors, cette structure permet de minimiser les mouvements de données au sein de MOREA et notamment le nombre d'accès mémoire et donc d'en atténuer l'impact sur la puissance de calcul et la dissipation énergétique du système. De plus, les gains obtenus sont maximisés grâce à une unité de génération d'adresses programmable dont l'architecture a été définie en fonction des caractéristiques des applications de traitement du signal et de l'image. Celle-ci intègre notamment un accélérateur matériel pour la génération de séquences d'adresses régulières. Cette architecture permet dès lors, comparativement à une solution programmable classique, d'améliorer significativement les performances de l'unité de génération d'adresses, d'un facteur 6 en terme de Millions d'Adresses générées Par Seconde (MAPS), tout en réduisant drastiquement sa consommation d'énergie de 96%.

Embedded system designers face multiple challenges in fulfilling the runtime requirements of programs. Effective scheduling of programs is required to extract as much parallelism as possible. These scheduling algorithms must also improve speedup after instruction-set extensions have occurred. Scheduling of dynamic code at run time is made more difficult when the static components of the program are scheduled inefficiently. This research aims to optimize a program’s static code at compile time. This is achieved with four algorithms designed to schedule code at the task and instruction level. Additionally, the algorithms improve scheduling using instruction set extended code on symmetrical homogeneous multiprocessor systems. Using these algorithms, we achieve speedups up to 3.86X over sequential execution for a 4-issue 2-processor system, and show better performance than recent heuristic techniques for small programs. Finally, the algorithms generate speedup values for a 64-point FFT that are similar to the test runs.

This report describes both evaluation and implementation of the new coming image compression standard JPEG XR. The intention is to determine if JPEG XR is an appropriate standard for IP based video surveillance purposes. Video surveillance, especially IP based video surveillance, currently has an increasing role in the security market. To be a good standard for surveillance, the video stream generated by the camera is required to be low bit-rate, low latency on the network and at the same time keep a high dynamic display range. The thesis start with a deep insightful study of JPEG XR encoding standard. Since the standard could have different settings,optimized settings are applied to JPEG XR encoder to fit the requirement of network video surveillance. Then, a comparative evaluation of the JPEG XR versusthe JPEG is delivered both in terms of objective and subjective way. Later, part of the JPEG XR encoder is implemented in hardware as an accelerator for further evaluation. SystemVerilog is the coding language. TSMC 40nm process library and Synopsys ASIC tool chain are used for synthesize. The throughput, area, power ofthe encoder are given and analyzed. Finally, the system integration of the JPEGXR hardware encoder to Axis ARTPEC-X SoC platform is discussed.

Syftet med föreliggande studie var att undersöka hur det kommer sig att vissa personer med ätstörningar väljer att starta en ätstörningsblogg samt hur de upplever sitt bloggande. Respondenterna bestod av fem kvinnor i åldrarna 23-35 år som bloggar om sina ätstörningar. En kvalitativ metod användes där semistrukturerade intervjuer genomfördes över telefon. Resultaten analyserades och tolkades med hjälp av känslan av sammanhang (KASAM) och copingteori. Resultaten visade att anledningarna till att starta en blogg var många, bl.a. kände respondenterna ett behov av en plats att ventilera sina tankar på, och att de genom att blogga om sina erfarenheter såg en möjlighet att hjälpa andra. Bloggen sågs också som ett sätt att kommunicera med sina anhöriga utan att behöva sitta ansikte mot ansikte. Bloggen upplevs medföra ökad social acceptans och den ses som ett positivt stöd i sjukdomen. Resultaten pekar på att bloggande kan ses som ett copingverktyg och att bloggen kan fungera som ett redskap för att begripa, hantera och se mening i ätstörningarna enligt komponenterna i KASAM. / The aim of the following study was to examine why some individuals who have been affected by eating disorders choose to write blogs and how they feel about this experience. The group of respondents consisted of five women aged 23-35, who currently write blogs about their eating disorders. A qualitative method was utilized by means of semi-structured interviews conducted over the telephone and then analyzed using sense of coherence and coping theory. The results showed that the main reasons to start a blog were seeing it as an outlet to vent emotions, a way to help others suffering from eating disorders and a means to communicate about problems without having to do so face to face. Furthermore the blog was viewed as a positive resource to deal with eating disorders and as a way of gaining social support. Blogging can thus be viewed as a coping tool and as a way to increase comprehensibility, manageability and meaningfulness according to the sense of coherence.

A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction. The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.

Syftet med uppsatsen var att undersöka hur det kan vara att leva med ADHD som vuxen inom tre områden; arbete, fritidsaktiviteter och vardagsliv, och på så vis öka förståelsen för dessa individer.  Som underlag för studien gjordes kvalitativa intervjuer med tre vuxna män med ADHD-diagnos. Resultatet från dessa intervjuer analyserades med hjälp av teorier om copingstrategier och KASAM.  Intervjumaterialet visade på en stor spridning av hur funktionsnedsättningen ADHD påverkade livet. Det var främst symptomen uppmärksamhetsstörning och hyperaktivitet som ledde till svårigheter i arbetsliv, fritid och vardagsliv. Svårigheterna yttrade sig dock på väldigt olika sätt. Symptomet hyperaktivitet upplevdes i vissa situationer som en tillgång. Eftersom ADHD påverkade intervjupersonerna olika gavs exempel på ett flertal copingstrategier. Det gavs också olika exempel på hur ADHD påverkade intervjupersonernas upplevelse av begriplighet, hanterbarhet och meningsfullhet. / The purpose of this paper was to examine life with ADHD as an adult in three areas: work, leisure activities and daily life, and thereby increase the understanding of these individuals. The empirical research of the study was interviews with three adult males with ADHD. The result from the interviews was analyzed using theories of coping strategies and SOC. The result revealed a width of how the disability ADHD affected the interviewee’s lives.  It was mainly the symptoms of inattention and hyperactivity that affected work, leisure and everyday life. The difficulties were manifested in very different ways. The symptom hyperactivity could in some situations be seen as a benefit. Since ADHD affected the interviewees in different ways a number of various coping strategies were given as examples of how the interviewees deal with stressful situations in live. Various examples of how ADHD affected the interviewee’s experience of SOC were reviled in the study.

Back, I. & Hörberg, A. (2009). En ordförandegrupps känsla av sammanhang. C-uppsats i pedagogik. Institution för pedagogik, didaktik och psykologi. Högskolan i Gävle. I den ekonomiska krisen som slår hårt mot industrin har fackföreningsordföranden och ledare en utsatt position i tider av personalneddragningar på grund av minskade orderingångar. Denna studies syfte är att undersöka en ordförandegrupps känsla av sammanhang och söka faktorer som påverkar känslan av sammanhang. Detta görs genom intervjuer och enkäter. I resultatet framgår att gruppens känsla av sammanhang är relativt högt trots hot och stress. En viktig orsak till den höga känslan av sammanhang i gruppen är den höga meningsfullheten och det sociala stödet gruppen har. Nyckelord: KASAM, chefsroll, fackföreningsordföranden, hälsofrämjande, ledare, stress, / Back. I & Hörberg, A. (2009). A group of trade union leader’s sense of coherence Ccomposition in Education. Department of pedagogy, didactics and psychology. University of  Gävle In the economic crisis which strikes hard against the industry, trade union chairmen and leaders have vulnerable positions. In times when companies needs to reduce the number of employees because of diminishing orders the organized labors get a large Burdon to help in the process. The aim of this study is to investigate a group of trade union leaders, find out their sense of coherence, also known as SOC., and to look for health factors. The results of interviews and questionnaires show that the sense of coherence in the group is on a relative high level in spite of threat and stress. A main reason to this high sense of coherence in the group is that they feel that their efforts are important and that they have support from the members.

As today's real-time embedded systems grow increasingly ubiquitous, rising complexity ensues as more and more functionalities are integrated. Market dynamics and competitiveness further constrict the technology-to-market time requirement, consequently pushing it to the very forefront of consideration during the development process. Traditional system development approaches could no longer efficiently cope with such formidable demands, and a paradigm shift has been perceived by many as a mandate. This thesis presents a novel platform-centric SoC design method that relies on a platform-based design to expedite the overall development process. The proposed approach offers a new perspective towards the complex systems design paradigm, and can attain the desired paradigm shift through extensive reuse and flexibility. It offers a unified communication means for all sectors involved in the development process: Semiconductor vendors can use it to publish their platform specifications; Tool vendors can use it to develop and/or enhance their tools; System developers can use it to efficiently develop the system. Key technologies are also identified, namely the Extensible Markup Language (XML) and the Unified Modeling Language (UML), that realize the proposed approach. This thesis extends XML to attain a standard means for modeling, and processing a large amount of reusable platform-related data. Additionally, it employs UML's own extension mechanism to derive a UML dialect that can be used to model real-time systems and characteristics. This UML dialect, i.e. the UML profile for Codesign Modeling Framework (UML-CMF), remains compliant to the UML standard. A sub-profile within the UML profile for Codesign Modeling Framework is also developed so as to furnish a means for efficient modeling of platforms, and that can be seamlessly integrated with other real-time modeling capabilities offered by the UML-CMF. Such an effort yields a robust UML-compliant language that is suitable for a general platform-based modeling and design. A practical use of the proposed approach is demonstrated through a powerful case study that applies the approach to develop a digital camera system. The results are comparatively presented against the SpecC approach in terms of cost metrics based on the COCOMO II model.

This dissertation deals with the development of RF MEMS switches with novel materials and micromachining techniques for the RF and microwave applications. To enable the integration of RF and microwave components on CMOS grade silicon, finite ground coplanar waveguide transmission line on CMOS grade silicon wafer were first studied using micromachining techniques. In addition, several RF MEMS capacitive switches were developed with novel materials. A novel approach for fabricating low cost capacitive RF MEMS switches using directly photo-definable high dielectric constant metal oxides was developed, these switches exhibited significantly higher isolation and load capacitances as compared to comparable switches fabricated using a simple silicon nitride dielectric. The second RF MEMS switch developed is on a low cost, flexible liquid crystal polymer (LCP) substrate. Its very low water absorption (0.04%), low dielectric loss and multi-layer circuit capability make it very appealing for RF Systems-On-a-Package (SOP). Also, a tunable RF MEMS switch on a sapphire substrate with BST as dielectric material was developed, the BST has a very high dielectric constant (>300) making it very appealing for RF MEMS capacitive switches. The tunable dielectric constant of BST provides a possibility of making linearly tunable MEMS capacitor-switches. For the first time a capacitive tunable RF MEMS switch with a BST dielectric and its characterization and properties up to 40 GHz was presented. Dielectric charging is the main reliability issue for MEMS switch, temperature study of dielectric polarization effect of RF MEMS was investigated in this dissertation. Finally, integration of two reconfigurable RF circuits with RF MEMS switches were discussed, the first one is a reconfigurable dual frequency (14GHz and 35 GHz) antenna with double polarization using RF MEMS switches on a multi-layer LCP substrate; and the second one is a center frequency and bandwidth tunable filter with BST capacitors and RF MEMS switches on sapphire substrate.

This thesis studies State-of-Charge (SOC) method for widely used lead-acid batteries and the most prospective lithium-ion batteries. First, the relationship between the battery capacity and the open-circuit-voltage under different charging/discharging currents is investigated based on the equivalent circuit. Experimental results indicate that the open-circuit-voltage of the lead-acid battery varies regularly with the charging/discharging current and the duration of time for the battery disconnected from the load. Accordingly, a dynamic open-circuit-voltage method in considerations the open-circuit-time and the previous operating current is capable of precisely estimating the battery capacity in a shorter time. As for the lithium-ion batteries, their charging/discharging characteristics reveal that the Coulomb/Ampere-Hour Counting method is capable of yielding accurate estimations. Finally, through the experiments that emulate practical operations, the SOC estimations of batteries are verified to demonstrate the effectiveness and accuracy of the proposed methods.