京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第18286号 / 工博第3878号 / 新制||工||1595(附属図書館) / 31144 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 白石 誠司, 准教授 浅野 卓 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第19710号 / 工博第4165号 / 新制||工||1642(附属図書館) / 32746 / 京都大学大学院工学研究科材料工学専攻 / (主査)教授 酒井 明, 教授 河合 潤, 教授 中村 裕之 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DGAM

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Parameter variations introduced by manufacturing imprecision are becoming more influential on circuit performance. This is especially the case in emerging nanoscale fabrics due to unconventional manufacturing steps (e.g., nano-imprint) and aggressive scaling. These parameter variations can lead to performance deterioration and consequently yield loss. Parameter variations are typically addressed pre-fabrication with circuit design targeting worst-case timing scenarios. However, this approach is pessimistic and much of performance benefits can be lost. By contrast, if parameter variations can be estimated post-manufacturing, adaptive techniques or reconfiguration could be used to provide more optimal level of tolerance. To estimate parameter variations during run-time, on-chip variation sensors are gaining in importance because of their easy implementation. In this thesis, we propose novel on-chip variation sensors to estimate variations in physical parameters for emerging nanoscale fabrics. Based on the characteristics of systematic and random variations, two separate sensors are designed to estimate the extent of systematic variations and the statistical distribution of random variations from measured fall and rise times in the sensors respectively. The proposed sensor designs are evaluated through HSPICE Monte Carlo simulations with known variation cases injected. Simulation results show that the estimation error of the systematic-variation sensor is less than 1.2% for all simulated cases; and for the random-variation sensor, the worst-case estimation error is 12.7% and the average estimation error is 8% for all simulations. In addition, to address the placement of on-chip sensors, we calculate sensor area and the effective range of systematic-variation sensor. Then using a processor designed in nanoscale fabrics as a target, an example for sensor placement is introduced. Based on the sensor placement, external noises that may affect the measured fall and rise times of outputs are identified. Through careful analysis, we find that these noises do not deteriorate the accuracy of the systematic-variation sensor, but affect the accuracy of the random-variation sensor. We believe that the proposed on-chip variation sensors in conjunction with post-fabrication compensation techniques would be able to improve system-level performance in nanoscale fabrics, which may be an efficient alternative to making worst-case assumptions on parameter variations in nanoscale designs.

The aim of this work is to make electrochemical metal nanowire growth a competitive method, being up to par with more standardized procedures, like e.g. lithography. This includes on the one hand the production of nanowires as reliable and reproducible parts, potentially suited for nanoelectronic circuit design. Therefore, this work presents a systematic investigation of the causes of nanowire branching, the necessary conditions to achieve straight growth and the parameters affecting the diameter of the wires. The growth of ultrathin (down to 15 nm), straight and unbranched platinum nanowires assembly is demonstrated. On the other hand, it is the objective to go beyond purely electronic applications. An examination of the crystallography of the wires reveals nanoclusters inside the wire with a common crystallographic orientation. The versatility of the wires is illustrated by implementing them into an impedimetric sensor capable of the detection of single nanoscaled objects, such as bacteria. / Die Zielstellung der vorliegenden Arbeit ist es, die elektrochemische Herstellung von metallischen Nanodrähten zu einer wettbewerbsfähigen Methode zu machen, die sich mit standardisierten Prozessen, wie z. B. der Lithographie messen kann. Dies beinhält auf der einen Seite die Produktion der Nanodrähte als zuverlässige und reproduzierbare Bauteile, die im nanoelektrischen Schaltungsdesign Verwendung finden können. Daher befasst sich diese Arbeit mit einer systematischen Untersuchung der Ursachen für die Verzweigung von Nanodrähten, den notwendigen Bedingungen um gerades Wachstum zu erlangen und mit den Parametern, die Einfluss auf den Durchmesser der Drähte haben. Der Wuchs von sehr dünnen (bis zu 15 nm), geraden und unverzweigten Nanodrähten aus Platin wird gezeigt. Auf der anderen Seite ist es erklärtes Ziel, über rein elektronische Anwendungen hinaus zu gehen. Eine Untersuchung der Kristallographie der Nanodrähte zeigt, dass die Drähte aus Nanopartikeln bestehen, die eine gemeinsame kristallographische Orientierung aufweisen. Die Vielseitigkeit der Drähte wird anhand einer Sensoranwendung gezeigt, mit der es möglich ist, einzelne nanoskalige Objekte (wie z. B. Bakterien) zu detektieren.

A process, called carbon nanotube templated microfabrication (CNT-M) makes high aspect ratio microstructures out of a wide variety of materials by growing patterned vertically aligned carbon nanotubes (VACNTs) as a framework and then infiltrating various materials into the frameworks by chemical vapor deposition (CVD). By using the CNT-M procedure, a partial Si infiltration of carbon nanotube frameworks results in porous three dimensional microscale shapes consisting of silicon-carbon nanotube composites. The addition of thin silicon shells to the vertically aligned CNTs (VACNTs) enables the fabrication of robust silicon nanostructures with edibility to design a wide range of geometries. Nanoscale dimensions are determined by the diameter and spacing of the resulting silicon/carbon nanotubes while microscale dimensions are controlled by the lithographic patterning of CNT growth catalyst. The characterization and application of the new silicon nanomaterial, silicon-carbon core-shell nanotube (Si/CNT) composite, is investigated thoroughly in the dissertation.The Si/CNT composite is used as thin layer chromatography (TLC) separations media with precise microscale channels for fluid flow control and nanoscale porosity for high analyte capacity. Chemical separations done on the CNT-M structured media outperform commercial high performance TLC media resulting from separation efficiency and retention factor. The Si/CNT composite is also used as an anode material for lithium ion batteries. The composite is assembled into cells and tested by cycling against a lithium counter electrode. This CNT-M structured composite provides an effective test bed for studying the effects of geometry (e.g. electrode thickness, porosity, and surface area) on capacity and cycling performance. A combination of high gravimetric, volumetric, and areal capacity makes the composite an enabling materials system for high performance Li-ion batteries.Last, a thermal annealing to the Si/CNT composite results in the formation of silicon carbide nanowires (SiCNWs). This combination of annealing and Si/CNTs yields a unique fabrication approach resulting in porous three dimensional silicon carbide structures with precise control over shape and porosity.

Bottom-up self-assembly can be used to create structures with sub-20 nm feature sizes or materials with advanced electrical properties. Here I demonstrate processes to enable such self-assembling systems including block copolymers and DNA origami, to be integrated into nanoelectronic devices. Additionally, I present a method which utilizes the high stability and electrical conductivity of graphene, which is a material formed using a bottom-up growth process, to create archival data storage devices. Specifically, I show a technique using block copolymer micelle lithography to fabricate arrays of 5 nm gold nanoparticles, which are chemically modified with a single-stranded DNA molecule and used to chemically attach DNA origami to a surface. Next, I demonstrate a method using electron beam lithography to control location of nanoparticles templated by block copolymer micelles, which can be used to enable precise position of DNA origami on a surface. To allow fabrication of conductive structures from a DNA origami template, I show a method using site-specific attachment of gold nanoparticles to and a subsequent metallization step to form continuous nanowires. Next, I demonstrate a long-term data storage method using nanoscale graphene fuses. Top-down electron beam lithography was used to pattern atomically thin sheets of graphene into nanofuses. To program the fuses, graphene is oxidized as the temperature of the fuse is raised via joule heating under a sufficiently high applied voltage. Finally, I investigate the effect of the fuse geometry and the electrical and thermal properties of the fuse material on the programming requirements of nanoscale fuses. Programming voltages and expected fuse temperatures obtained from finite element analysis simulations and a simple analytical model were compared with fuses fabricated from tellurium, a tellurium alloy, and tungsten.

In this work we investigated fabrication of semiconductor nanomaterials and evaluated their potential for photo-chemical and photovoltaic applications. We investigated two different II-VI semiconductor nanomaterial systems; (i) ZnO oriented nanowire arrays non-epitaxially grown from a substrate; and (ii) colloidal CdTe nanotetrapods synthesized by solution-based thermal decomposition of organo-metallic precursors. In both the cases our main focus has been optimizing material synthesis for improving potential applications based on photon-electron interactions. We have studied the synthesis of vertically aligned ZnO nanowire arrays (NWA), by a wet chemical process on various substrates. The synthesis is based on epitaxial growth of ZnO seed-layer on a substrate in a chemical bath consisting of an aqueous solution of zinc nitrate and hexamethylenetetramine (HMT). We have suggested an additional role played by HMT during the synthesis of ZnO nanowire arrays. We have also extended this synthesis method to fabricate hierarchical nanostructures of nanofibers of poly-L-lactide acting as a substrate for the radially oriented growth of ZnO nanowires. The combination of high surface area of the nanofibrous substrate with the flexibility of the PLLA-ZnO hierarchical nanostructure enabled the proof-of-principle demonstration of a ‘continuous-flow’ water treatment system that could effectively decompose single and combination of known organic pollutants in water, as well as render common waterborne bacteria nonviable. We have studied another chemical synthesis that is commonly used for size controlled synthesis of colloidal quantum dots, which was modified to obtain anisotropic nanocrystals mainly for CdE (E=S, Se, Te) compositions. In this work we demonstrate by use of oleic acid (instead of alkylphosphonic acids) it is possible to synthesize CdTe and CdSe nanotetrapods at much lower temperatures (~180 ºC) than what is commonly reported in the literature, with significantly different  formation mechanism in the low-temperature reaction. Finally, we have performed preliminary photoconduction measurements with CdTe nanotetrapods using gold ‘nanogap’ electrodes fabricated in-house, and obtain up to 100 times enhancement in current levels in the I–V measurements under illumination with a white light source. / QC20100607

The semiconductor industry scaling has mainly been driven by Moore's law, which states that the number of transistors on a single chip should double every year and a half to two years. Beyond 2011, when the channel length of the Metal Oxide Field effect transistor (MOSFET) approaches 16 nm, the scaling of the planar MOSFET is predicted to reach its limit. Consequently, a departure from the current planar MOSFET on bulk silicon substrate is required to push the scaling limit further while maintaining electrostatic control of the gate over the channel. Alternative device structures that allow better control of the gate over the channel such as reducing short channel effects, and minimizing second order effects are currently being investigated. Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to parasitic effects from the bulk. The doping of the source and drain regions and the redistribution of the dopants in the channel greatly impact the electrical characteristics of the fabricated device. Thus, in nano-scale and reduced dimension transistors, a tight control of doping levels and formation of pn junctions is required. Therefore, deeper understanding of the lateral component of the diffusion mechanisms and interface effects in these lower dimensional structures compared to the bulk is necessary. This work focuses on studying the dopant diffusion mechanisms in Silicon nanomembranes (2D), nanoribbons (â 1.Xâ D), and nanowires (1D). This study also attempts to benchmark the 1D and 2D diffusion against the well-known bulk (3D) diffusion mechanisms. / Master of Science

Electronic band structure of various crystal orientations of relaxed and strained bulk, 1D and 2D confined semiconductors are investigated using nonlocal empirical pseudopotential method with spin-orbit interaction. For the bulk semiconductors, local and nonlocal pseudopotential parameters are obtained by fitting transport-relevant quantities, such as band gap, effective masses and deformation potentials, to available experimental data. A cubic-spline interpolation is used to extend local form factors to arbitrary q and the resulting transferable local pseudopotential V(q) with correct work function is used to investigate the 1D and 2D confined systems with supercell method. Quantum confinement, uniaxial and biaxial strain and crystal orientation effects of the band structure are investigated. Regarding the transport relavant quantities, we have found that the largest ballistic electron conductance occurs for compressively-strained large-diameter [001] wires while the smallest transport electron effective mass is found for larger-diameter [110] wires under tensile stress.