The recent advancement of superconducting nano devices has allowed for making a Superconducting Nanowire Single Photon Detector (SNSPD), whose extraordinary features have strongly motivated the research community to exploit it in many practical applications. In this thesis, an experimental setup for testing the SNSPD has been established. It contains an in-house packaging that meets the requirements of RF/microwave and optoelectronic characterizations. The quantum efficiency and detection efficiency measurements have confirmed that our approach is satisfactory. The dark count performance has reached the anticipated level. The factors affecting rise and fall times of the photoresponses are addressed. Based on the successful setup, the characterizations including dc, small signal ac measurements have been undertaken. The measurements are aimed at quantitatively investigating Cooper pair density in the superconducting nanowire. The experimental method involves a two-step, small signal S-parameter measurement either in the presence or absence of optical powers. The subsequent measurements by varying the temperature and dc bias current have achieved remarkable understanding on the physical properties of SNSPD nanowires. Then, the electrically induced nonlinearity is studied via the large signal RF and Microwave measurements. The experiments are a set of one-tone and two-tone measurements, in which either the RF driving power is varied at a fixed frequency, or vice versa. Two major nonlinear microwave circuit analysis methods, i.e. time-domain transient and hybrid-domain harmonic balance analysis, are employed. The simulation result reveals the optimized conditions of reaching the desired nonlinearity. Finally, we have successfully measured the optoelectronic mixing products in an electrically pumped optoelectronic mixer, which has identical structures as that of the SNSPD. The experiments confirm that this mixer is not only sensitive to the classical light intensities, but also to that of the single photon level. Meanwhile, the quantum conversion matrices is derived to interpret the quantum optoelectronic mixing effects.

The constant trend of device miniaturization along with ever-growing list of unusual behaviour of nanoscale materials has fuelled the recent research in fabrication and applications of ultrathin (~2 nm diameter) nanowires. Although semiconductor nanowires of this dimension is well-researched, molecular-scale single-crystalline metal nanowires have not been addressed in details. Such single crystalline Au nanowires are formed by oriented attachment of Au nanoparticles along [111] direction. A very low concentration of extended defects in these wires result in a high electrical conductivity, making them ideal for nanoscale interconnects. Other metal nanowires, e.g. Ag and Cu, have very low absorption co-efficient useful for fabrication of transparent conducting films. On the other hand, because of the reduced dimensions, there exists a tantalizing possibility of dominating quantum effects leading to their application in sensing and actuation. Also, speaking in terms of atomic structure, these systems suffer from intense surface stress, and the atomistic picture can be drastically different from bulk. Thus, although a myriad of applications are possible with ultrathin metal nanowires, a rigorous systematic knowledge of their atomic and electronic structure is not yet available. This thesis is the first one to model such computationally demanding systems with emphasis on their possible applications. In this thesis, we have explored various structural and electronic aspects of one-dimensional ultrathin nanowires with ab initio density functional theory coupled with experiments. The merit of Au nanowires has been tested as nanoscale interconnects. From atomistic point of view, these FCC Au nanowires exhibit an intriguing relaxation mechanism, which has been explored by both theory and experiment. The primary factor governing the relaxation mechanism was found to be the anisotropic surface stress of the bounding facets, and it is extended to explain the relaxation of other metallic nanowires. Our studies suggest that AuNWs of this dimension show semiconductor-like sensitivity towards small chemical analytes and can be used as nanoscale sensors. Also, we have found that further reducing the diameter of the Au-nanowires leads to opening of a band gap.

Pas de résumé en français / Plasmonic circuitry is considered as a promising solution-effectivetechnology for miniaturizing and integrating the next generation ofoptical nano-devices. The realization of a practical plasmonic circuitry strongly depends on the complete understanding of the propagation properties of two key elements: surface plasmons and electrons. The critical part constituting the plasmonic circuitry is a waveguide which can sustain the two information-carriers simultaneously. Therefore, we present in this thesis the investigations on the propagation of surface plasmons and the co-propagation of surface plasmons and electrons in single crystalline metal nanowires. This thesis is therefore divided into two parts. In the first part, we investigate surface plasmons propagating in individual thick penta-twinned crystalline silver nanowires using dual-plane leakage radiation microscopy. The effective index and the losses of the mode are determined by measuring the wave vector content of the light emitted in the substrate. Surface plasmon mode is determined by numerical simulations and an analogy is drawn with molecular orbitals compound with similar symmetry. Leaky and bound modes selected by polarization inhomogeneity are demonstrated. We further investigate the effect of wire geometry (length, diameter) on the effective index and propagation losses. On the basis of the results obtained during the first part, we further investigate the effect of an electron flow on surface plasmon properties. We investigate to what extend surface plasmons and current-carrying electrons interfere in such a shared circuitry. By synchronously recording surface plasmons and electrical output characteristics of single crystalline silver and gold nanowires, we determine the limiting factors hindering the co-propagation of electrical current and surface plasmons in these nanoscale circuits. Analysis of wave vector distributions in Fourier images indicates that the effect of current flow on surface plasmons propagation is reflected by the morphological change during the electromigration process. We further investigate the possible crosstalk between co-propagating electrons and surface plasmons by applying alternating current bias

Die kontinuierliche Skalierung der planaren MOSFETs war in den vergangenen 40 Jahren der Schlüssel, um die Bauelemente immer kleiner und leistungsfähiger zu gestalten. Hinzu kamen Techniken zur mechanischen Verspannung, Verfahren zur Kurzzeitausheilung, die in-situ-dotierte Epitaxie und neue Materialien, wie das High-k-Gateoxid in Verbindung mit Titannitrid als Gatemetall. Jedoch erschwerten Kurzkanaleffekte und eine zunehmende Streuung der elektrischen Eigenschaften die Verkleinerung der planaren Transistoren erheblich. Somit gelangten die planaren MOSFETs mit der aktuellen 28 nm-Technologie teilweise an die Grenzen ihrer Funktionalität. Diese Arbeit beschäftigt sich daher mit der Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie, welche eine bessere Steuerfähigkeit des Gatekontaktes aufweisen und somit die Fortführung der Skalierung ermöglichen. Zudem standen die Anforderungen eines stabilen und kostengünstigen Herstellungsprozesses als Grundvoraussetzung zur Übernahme in die Volumenproduktion stets mit im Vordergrund. Die Simulationen der Tri-Gate-Transistoren stellten dabei den ersten Schritt hin zu einer Multi-Gate-Technologie dar. Ihre Prozessabfolge unterscheidet sich von den planaren Transistoren nur durch die Formierung der Finnen und bietet damit die Möglichkeit eines hybriden 22 nm-Prozesses. Am Beispiel der Tri-Gate-Transistoren wurden zudem die Auswirkungen der Kristallorientierung, der mechanischen Verspannung und der Überlagerungseffekte es elektrischen Feldes auf die Leistungsfähigkeit von Multi-Gate-Strukturen analysiert. Im nächsten Schritt wurden Transistoren mit vollständig verarmten Kanalgebieten untersucht. Sie weisen aufgrund einer niedrigen Kanaldotierung eine Volumeninversion, eine höhere Ladungsträgerbeweglichkeit und eine geringere Anfälligkeit gegenüber der zufälligen Dotierungsfluktuation auf, welche für leistungsfähige Multi-Gate-Transistoren entscheidende Kriterien sind. Zu den betrachteten Varianten zählen die planaren ultradünnen SOI-MOSFETs, die klassischen FinFETs mit schmalen hohen Finnen und die vertikalen Nanowire-Transistoren. Anschließend wurden die Vor- und Nachteile der verschiedenen Transistorstrukturen für eine mittel- bis langfristige industrielle Nutzung betrachtet. Dazu erfolgte eine Analyse der statistischen Schwankungen und eine Skalierung hin zur 14 nm-Technologie. Eine Zusammenfassung aller Ergebnisse und ein Ausblick auf die mögliche Übernahme der Konzepte in die Volumenproduktion schließen die Arbeit ab.:Symbol- und Abkürzungsverzeichnis 1 Einleitung 2 Grundlagen und Entwicklung der CMOS-Technologie 2.1 Planare Transistoren 2.1.1 Theoretische Grundlagen von MOSFETs 2.1.2 Skalierung und Kurzkanalverhalten planarer Transistoren 2.1.3 Mechanische Verspannung von Silizium 2.1.4 Techniken zur mechanischen Verspannung 2.2 Multi-Gate-Transistoren 2.2.1 Multi-Gate-Strukturen 2.2.2 Überlagerungseffekte 2.2.3 Quanteneffekte 2.3 Stand der Technik 3 Grundlagen der Simulation 3.1 Prozesssimulation 3.1.1 Abscheiden und Abtragen von Schichten 3.1.2 Implantation 3.1.3 Thermische Ausheilung mit Diffusion 3.2 Bauelementesimulation 3.2.1 Grundgleichungen und Ladungsträgertransport 3.2.2 Bandlückenverengung 3.2.3 Generation und Rekombination 3.2.4 Ladungsträgerbeweglichkeit 3.2.5 Effekte der mechanischen Verspannung 3.2.6 Ladungsträgerquantisierung 3.3 Kalibrierung der Modellparameter 3.3.1 Prozessparameter 3.3.2 Modellparameter 4 Planare Transistoren auf Basis einer 22 nm-Technologie 4.1 Transistoraufbau 4.1.1 Replacement-Gate-Prozess 4.1.2 In-situ-dotierte Source-Drain-Gebiete 4.1.3 Haloimplantation 4.1.4 Elemente der mechanischen Verspannung 4.2 Charakterisierung des elektrischen Verhaltens 4.2.1 Stationäres Verhalten 4.2.2 Gatesteuerung und Kurzkanaleffekte 4.2.3 Dynamisches Verhalten 5 Tri-Gate-Transistoren 5.1 Prozessintegration und Transistoraufbau 5.1.1 Anforderungen an hochintegrierte Schaltkreise 5.1.2 Hybride CMOS-Technologie 5.1.3 Strukturierung der Finne 5.1.4 Geometrieabhängiges Dotierungsprofil 5.2 Charakterisierung des elektrischen Verhaltens 5.2.1 Stationäres Verhalten 5.2.2 Kurzkanaleffekte und Gatesteuerung 5.2.3 Eckeneffekt 5.2.4 Eckenimplantation 5.2.5 Finnengeometrie 5.2.6 Dynamisches Verhalten 5.3 Optimierung der Tri-Gate-Struktur 5.3.1 Gestaltung der epitaktischen Source-Drain-Gebiete 5.3.2 Mechanisch verspanntes Isolationsoxid 5.3.3 Substratorientierung 6 Transistoren mit vollständig verarmtem Kanal 6.1 Ultra-Dünne-SOI-MOSFETs 6.1.1 Prozessintegration 6.1.2 Charakterisierung des elektrischen Verhaltens 6.2 FinFETs 6.2.1 Prozessintegration 6.2.2 Charakterisierung des elektrischen Verhaltens 6.3 Vertikale Nanowire-MOSFETs 6.3.1 Prozessintegration 6.3.2 Strukturierung des Aktivgebiets 6.3.3 Charakterisierung des elektrischen Verhaltens 6.3.4 Asymmetrisches Dotierungsprofil 6.3.5 Mechanische Verspannung 7 Skalierung und statistische Schwankungen der Strukturen 7.1 Skalierung zur 14 nm-Technologie 7.1.1 Leistungsfähigkeit 7.1.2 Kurzkanalverhalten und Steuerfähigkeit 7.2 Statistische Schwankungen 7.2.1 Impedanz-Feld-Methode 7.2.2 Zufällige Dotierungsfluktuation 7.2.3 Fixe Ladungen im Oxid 7.2.4 Metall-Gate-Granularität 7.2.5 Geometrische Variationen 7.2.6 Kombination der Störquellen 8 Zusammenfassung und Ausblick Anhang Literaturverzeichnis Danksagung Acknowledgement / Within the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work.:Symbol- und Abkürzungsverzeichnis 1 Einleitung 2 Grundlagen und Entwicklung der CMOS-Technologie 2.1 Planare Transistoren 2.1.1 Theoretische Grundlagen von MOSFETs 2.1.2 Skalierung und Kurzkanalverhalten planarer Transistoren 2.1.3 Mechanische Verspannung von Silizium 2.1.4 Techniken zur mechanischen Verspannung 2.2 Multi-Gate-Transistoren 2.2.1 Multi-Gate-Strukturen 2.2.2 Überlagerungseffekte 2.2.3 Quanteneffekte 2.3 Stand der Technik 3 Grundlagen der Simulation 3.1 Prozesssimulation 3.1.1 Abscheiden und Abtragen von Schichten 3.1.2 Implantation 3.1.3 Thermische Ausheilung mit Diffusion 3.2 Bauelementesimulation 3.2.1 Grundgleichungen und Ladungsträgertransport 3.2.2 Bandlückenverengung 3.2.3 Generation und Rekombination 3.2.4 Ladungsträgerbeweglichkeit 3.2.5 Effekte der mechanischen Verspannung 3.2.6 Ladungsträgerquantisierung 3.3 Kalibrierung der Modellparameter 3.3.1 Prozessparameter 3.3.2 Modellparameter 4 Planare Transistoren auf Basis einer 22 nm-Technologie 4.1 Transistoraufbau 4.1.1 Replacement-Gate-Prozess 4.1.2 In-situ-dotierte Source-Drain-Gebiete 4.1.3 Haloimplantation 4.1.4 Elemente der mechanischen Verspannung 4.2 Charakterisierung des elektrischen Verhaltens 4.2.1 Stationäres Verhalten 4.2.2 Gatesteuerung und Kurzkanaleffekte 4.2.3 Dynamisches Verhalten 5 Tri-Gate-Transistoren 5.1 Prozessintegration und Transistoraufbau 5.1.1 Anforderungen an hochintegrierte Schaltkreise 5.1.2 Hybride CMOS-Technologie 5.1.3 Strukturierung der Finne 5.1.4 Geometrieabhängiges Dotierungsprofil 5.2 Charakterisierung des elektrischen Verhaltens 5.2.1 Stationäres Verhalten 5.2.2 Kurzkanaleffekte und Gatesteuerung 5.2.3 Eckeneffekt 5.2.4 Eckenimplantation 5.2.5 Finnengeometrie 5.2.6 Dynamisches Verhalten 5.3 Optimierung der Tri-Gate-Struktur 5.3.1 Gestaltung der epitaktischen Source-Drain-Gebiete 5.3.2 Mechanisch verspanntes Isolationsoxid 5.3.3 Substratorientierung 6 Transistoren mit vollständig verarmtem Kanal 6.1 Ultra-Dünne-SOI-MOSFETs 6.1.1 Prozessintegration 6.1.2 Charakterisierung des elektrischen Verhaltens 6.2 FinFETs 6.2.1 Prozessintegration 6.2.2 Charakterisierung des elektrischen Verhaltens 6.3 Vertikale Nanowire-MOSFETs 6.3.1 Prozessintegration 6.3.2 Strukturierung des Aktivgebiets 6.3.3 Charakterisierung des elektrischen Verhaltens 6.3.4 Asymmetrisches Dotierungsprofil 6.3.5 Mechanische Verspannung 7 Skalierung und statistische Schwankungen der Strukturen 7.1 Skalierung zur 14 nm-Technologie 7.1.1 Leistungsfähigkeit 7.1.2 Kurzkanalverhalten und Steuerfähigkeit 7.2 Statistische Schwankungen 7.2.1 Impedanz-Feld-Methode 7.2.2 Zufällige Dotierungsfluktuation 7.2.3 Fixe Ladungen im Oxid 7.2.4 Metall-Gate-Granularität 7.2.5 Geometrische Variationen 7.2.6 Kombination der Störquellen 8 Zusammenfassung und Ausblick Anhang Literaturverzeichnis Danksagung Acknowledgement

Numerical simulations of current-voltage characteristics of nanowire CdS/CdTe solar cells are performed as a function of temperature using SCAPS-1D. This research compares the experimental current-voltage (I-V) characteristics with the numerical (I-V) simulations obtained from SCAPS-1D at various temperatures. Various device parameters were studied which can affect the efficiency of the nanowire-CdS/CdTe solar cell. It was observed that the present simulated model explains the important effects of these solar cell devices, such as the crossover and the rollover effect. It was shown that the removal of defect in i-SnO2 is responsible for producing the crossover effect. In the past, the rollover effect has been explained by using back to back diode model in the literature. In this work, simulations were performed in order to validate this theory. At the back electrode, the majority carrier barrier height was varied from 0.4 to 0.5 eV, the curve corresponding to the 0.5 eV barrier showed a strong rollover effect, while this effect disappeared when the barrier was reduced to 0.4 eV. Thus, it was shown that the change of barrier height at the contact is a critical parameter in the rollover effect.

Die mechanischen Eigenschaften eines Materials spielen eine entscheidende Rolle für mögliche Anwendungen. Für nanoskalige Metalle ist lange bekannt, dass sich deren mechanischen Eigenschaften von ihren bulk-Gegenstücken stark unterscheiden. In bulk-Metallen wird die Verformung durch die Wechselwirkung vorhandener Versetzungen kontrolliert. Dies erweist sich scheinbar auf der Nanoebene als weniger zutreffend, da nur wenige oder keine Versetzungen in nanoskaligen Proben vorhanden sind und diese einfach aus der Probe herauslaufen können, ohne dass es vorher zu einer Wechselwirkung kommt. Die Verformung wird dann bestimmt durch die Nukleation neuer Versetzungen. In dieser Arbeit wurde die Verformung von Gold-Nanodrähten mit einem Durchmesser zwischen 50 und 150nm, die entweder einkristallin oder entlang ihrer Länge verzwillingt waren, untersucht. Auf der einen Seite erfolgte die Durchführung der Versuche in-situ im Transmissionselektronenmikroskop, um die Entwicklung der Defektmorphologie direkt beobachten zu können. Auf der anderen Seite wurden ebenfalls Tests in-situ im Rasterelektronenmikroskop mit einem neu entwickelten Aufbau durchgeführt und dabei das Spannungs-Dehnungs-Verhalten der Nanodrähte analysiert. Sämtliche Nanodrähte zeigten anfänglich ein elastisches Verhalten mit einem Elastizitätsmodul, das größenunabhängig war und nahe an dem entsprechenden Wert für Bulk-Gold lag. Mit Beginn der plastischen Verformung entstehen planare Defekte homogen verteilt entlang der Drähte, sowohl bei einkristallinen als auch verzwillingten Drähten. Zusammen mit der gemessenen Nukleationsspannung zeigte dies eine gute Übereinstimmung mit existierenden Modellen für die Oberflächennukleation von leading-Partialversetzungen, die auf klassischer Nukleationstheorie basieren. Mit weiterer Verformung kommt es ebenfalls zur Nukleation von trailing-Partialversetzungen, wodurch bereits entstandene planare Defekte wieder verschwinden und im Fall von verzwillingten Drähten volle Versetzungen gespeichert werden. Da die Nukleation von trailing-Partialversetzungen durch die existierenden Modelle nicht vorhergesagt wird, öffnet diese Beobachtung neue Fragen, ob klassische Nukleationstheorie in der Lage ist, die Nukleation von Versetzungen korrekt darzustellen.

In this dissertation I present results on our efforts to increase the sensitivity and selectivity of silicon nanowire ion-sensitive field-effect transistors for the detection of biomarkers, as well as a novel method for wireless power transfer based on metamaterial rectennas for their potential use as implantable sensors. The sensing scheme is based on changes in the conductance of the semiconducting nanowires upon binding of charged entities to the surface, which induces a field-effect. Monitoring the differential conductance thus provides information of the selective binding of biological molecules of interest to previously covalently linked counterparts on the nanowire surface. In order to improve on the performance of the nanowire sensing, we devised and fabricated a nanowire Wheatstone bridge, which allows canceling out of signal drift due to thermal fluctuations and dynamics of fluid flow. We showed that balancing the bridge significantly improves the signal-to-noise ratio. Further, we demonstrated the sensing of novel melanoma biomarker TROY at clinically relevant concentrations and distinguished it from nonspecific binding by comparing the reaction kinetics. For increased sensitivity, an amplification method was employed using an enzyme which catalyzes a signal-generating reaction by changing the redox potential of a redox pair. In addition, we investigated the electric double layer, which forms around charges in an electrolytic solution. It causes electrostatic screening of the proteins of interest, which puts a fundamental limitation on the biomarker detection in solutions with high salt concentrations, such as blood. We solved the coupled Nernst-Planck and Poisson equations for the electrolyte under influence of an oscillating electric field and discovered oscillations of the counterion concentration at a characteristic frequency. In addition to exploring different methods for improved sensing capabilities, we studied an innovative method to supply power to implantable biosensors wirelessly, eliminating the need for batteries. A metamaterial split ring resonator is integrated with a rectifying circuit for efficient conversion of microwave radiation to direct electrical power. We studied the near-field behavior of this rectenna with respect to distance, polarization, power, and frequency. Using a 100 mW microwave power source, we demonstrated operating a simple silicon nanowire pH sensor with light indicator.

Esse trabalho de mestrado teve como estudo o transistor Túnel-FET (TFET) fabricado em estrutura de nanofio de silício. Este estudo foi feito de forma teórica (simulação numérica) e experimental. Foram estudadas as principais características digitais e analógicas do dispositivo e seu potencial para uso em circuitos integrados avançados para a próxima década. A análise foi feita através da extração experimental e estudo dos principais parâmetros do dispositivo, tais como inclinação de sublimiar, transcondutância (gm), condutância de saída (gd), ganho intrínseco de tensão (AV) e eficiência do transistor. As medidas experimentais foram comparadas com os resultados obtidos pela simulação. Através do uso de diferentes parâmetros de ajuste e modelos de simulação, justificou-se o comportamento do dispositivo observado experimentalmente. Durante a execução deste trabalho estudou-se a influência da escolha do material de fonte no desempenho do dispositivo, bem como o impacto do diâmetro do nanofio nos principais parâmetros analógicos do transistor. Os dispositivos compostos por fonte de SiGe apresentaram valores maiores de gm e gd do que aqueles compostos por fonte de silício. A diferença percentual entre os valores de transcondutância para os diferentes materiais de fonte variou de 43% a 96%, sendo dependente do método utilizado para comparação, e a diferença percentual entre os valores de condutância de saída variou de 38% a 91%. Observou-se também uma degradação no valor de AV com a redução do diâmetro do nanofio. O ganho calculado a partir das medidas experimentais para o dispositivo com diâmetro de 50 nm é aproximadamente 45% menor do que o correspondente ao diâmetro de 110 nm. Adicionalmente estudou-se o impacto do diâmetro considerando diferentes polarizações de porta (VG) e concluiu-se que os TFETs apresentam melhor desempenho para baixos valores de VG (houve uma redução de aproximadamente 88% no valor de AV com o aumento da tensão de porta de 1,25 V para 1,9 V). A sobreposição entre porta e fonte e o perfil de dopantes na junção de tunelamento também foram analisados a fim de compreender qual combinação dessas características resultariam em um melhor desempenho do dispositivo. Observou-se que os melhores resultados estavam associados a um alinhamento entre o eletrodo de porta e a junção entre fonte e canal e a um perfil abrupto de dopantes na junção. Por fim comparou-se a tecnologia MOS com o TFET, obtendo-se como resultado um maior valor de AV (maior do que 40 dB) para o TFET. / This Master thesis focused in the study of the NW-TFET. The study was performed either by simulation as by experimental measurements. The main digital and analog characteristics of the device and its potential for use in advanced integrated circuits for the next decade were studied. The analysis was performed by extracting and studying the devices main parameters, such as subthreshold swing, transconductance (gm), output conductance (gd), intrinsic voltage gain (AV) and transistor efficiency. The experimental measurements were compared with the results obtained by simulation. Utilizing different simulation fitting parameters and models, the device behavior (observed in the experimental measurements) was understood and explained. During the execution of this work, either the influence of the source material on the device performance, as the impact of the nanowire diameter on the transistor main analog parameters, were studied. The devices with SiGe source presented higher values of gm and gd than those with silicon source. The percentual difference among the values of transconductance for the different source materials varied from 43% to 96%, being dependent on the method utilized for the comparison, and the percentual difference among the values of output conductance varied from 38% to 91%. A degradation of AV was also observed with the nanowire diameter reduction. The gain calculated from the experimental measurements for the device with 50 nm of diameter is approximately 57% lower than the gain corresponding to the diameter of 110 nm. Furthermore, the impact of the diameter considering different gate biases (VG) was analysed. It was concluded that TFETs show improved performance for lower values of VG (a reduction of approximately 88% of AV was observed for an increase of the gate voltage from 1.25 V to 1.9 V). The gate/source overlap length and the dopant profile at the tunneling junction were also analyzed in order to understand which combination of this features would result in a better performance of the device. It was observed that the best results were related to an alignment between the gate electrode and the source/channel junction and to an abrupt dopant profile at the junction. Finally, the MOS technology was compared with TFET, resulting in a higher AV (higher than 40 dB) for the TFET.

Les nanofils de silicium et de germanium présentent un fort potentiel technologique, d’autant plus important que leur position et leur taille sont contrôlées. Dans le cadre de cette thèse, la croissance de ces nano-objets a été réalisée par dépôt chimique en phase vapeur sous ultravide à l’aide d’un catalyseur d’or via le mécanisme vapeur-liquide-solide.Dans un premier temps, différentes techniques, le démouillage d’un film mince, l’évaporation par faisceau d’électrons et l’épitaxie par jet moléculaire, ont été mises en œuvre pour l’obtention du catalyseur métallique pour la croissance des nanofils.Dans un deuxième temps, la cinétique de croissance des nanofils de silicium a été étudiée en fonction de la pression, de la température de croissance et du diamètre des gouttes. Le gaz précurseur qui a été utilisé est le silane. Cette étude a permis de déterminer un diamètre critique de changement de direction de croissance, au-dessus duquel les nanofils sont épitaxiés sans défauts cristallins et préférentiellement selon la direction <111>. Le diamètre critique a été estimé à 80 nm. La cinétique de croissance en fonction de la pression a pu être interprétée de façon satisfaisante par la relation de Gibbs-Thomson. Ceci a permis la détermination du coefficient de collage des molécules de silane sur la surface de l'or et la pression de vapeur saturante du silicium P∞. Le changement morphologique de la section du nanofil et la distribution de nanoclusters d’or sur les parois ont été aussi détaillé à l’aide d’analyses par microscopie électronique en transmission.L’intégration des nanofils dans un dispositif nécessite de pouvoir les connecter. Pour les localiser et les orienter, un procédé basé sur le procédé d’oxydation localisée du silicium est proposé, pour former des ouvertures Si(111), à partir d’un substrat Si(001). Les gouttes d’or sont alors localisées dans ces ouvertures et vont servir à la croissance de nanofils orientés suivant une seule des directions [111]. Enfin, la cinétique de croissance de nanofils de germanium a été étudié. La limitation de l’utilisation du germane dilué à 10% dans l’hydrogène dans notre système d’épitaxie UHV-CVD a été démontrée. Compte tenu de notre dispositif expérimental, le gaz précurseur a été changé pour du digermane dilué à 10% dans de l’hydrogène afin de favoriser une croissance verticale de nanofils de Ge. Ceci nous a permis d’élaborer des nanofils de Ge avec des vitesses de croissance pouvant atteindre 100 nm/min. Des analyses structurales montrent l’existence d’un évasement des nanofils. Ceci est engendré par la présence d’une croissance latérale qui augmente avec la température. Comme dans le cas des nanofils de Si, nous observons la présence de l’or sur les parois latérales des nanofils. Cependant la présence de l’or est limitée à la partie supérieure des nanofils. Cette diffusion des nanoclusters d’or sur les parois peut être diminuée en augmentant la pression de croissance. En outre, l’étude de la vitesse de croissance des nanofils de Ge en fonction du rayon des gouttes d’or a permis de déterminer un rayon critique de 6 nm en dessous duquel la croissance de nanofil ne peut avoir lieu. Ce résultat a été interprété à l’aide d’un modèle basé sur l’effet Gibbs-Thomson et prenant comme hypothèse que l’étape limitante dans la croissance vapeur-liquide-solide est l’adsorption et l’évaporation du germanium. / Silicon and germanium nanowires have a high technological potential, which makes them more interesting when their position and size are controlled. As part of this thesis, the growth was achieved by chemical vapor deposition using a gold catalyst through the vapor-liquid-solid mechanism.Initially, various techniques such as dewetting, electron beam evaporation and molecular beam epitaxy to obtain the metal catalyst for the growth of nanowires were performed.In a second step, the growth kinetics of silicon nanowires has been studied as a function of pressure, temperature and catalyst diameter. Silane was used as precursor gas. A critical diameter change of direction of growth and above which the nanowires grow without crystal defects and preferentially in the direction <111> was estimated at 80 nm. The growth kinetics depending on the pressure could be explained by the Gibbs-Thomson. This allowed the determination of the adsorption coefficient of silane molecules on the surface of gold and the saturated vapor pressure of silicon P∞. The morphological change of the section of the nanowire and the distribution of gold nanoclusters on their walls were also detailed analysis using transmission electron microscopy.The integration of nanowires into devices requires to connect them. A process based on the method of local oxidation of silicon is proposed to form Si(111) seeds, from Si(001) substrate. Gold droplets are then located in these seeds and are used to grow nanowires oriented along one of the directions [111].Finally, the growth kinetics of germanium nanowires was studied. Restrictions on the use of 10% germane diluted in hydrogen in our system epitaxy UHV-CVD has been demonstrated. Given our experimental setup, the precursor gas was changed to the digermane diluted to 10% in hydrogen to promote vertical growth of Ge nanowires. This enabled us to develop Ge nanowires with growth rates up to 100 nm / min. Structural analysis showed the existence of a tapering of the nanowires. This is caused by the presence of lateral growth which increases with temperature. As in the case of Si nanowires, gold nanoclusters were observed on the sidewalls of the nanowires. However, the presence of gold is limited to the top of the nanowires. This diffusion of gold nanoclusters on the walls can be reduced by increasing the growth pressure. In addition, the variation of the speed of growth of Ge nanowires according to the radius of drops of gold has identified a critical radius of 6 nm below which the nanowire growth can occur. This result was interpreted using a model based on the Gibbs-Thomson effect and assuming that the limiting step in the vapor-liquid-solid growth is adsorption and evaporation of germanium.

Esse trabalho tem como objetivo estudar o comportamento de transistores de camada de silício e óxido enterrado ultrafinos (UTBB SOI nMOSFET) e transistores de nanofios horizontais com porta ômega ? (?G NW SOI MOSFET) com ênfase na variação da tensão aplicada no substrato (VGB). As análises foram feitas através de medidas experimentais e simulações numéricas. Nos dispositivos UTBB SOI nMOSFET foram estudados dispositivos com e sem implantação de plano de terra (GP), de três diferentes tecnologias, e com diferentes comprimentos de canal. A partir do modelo analítico de tensão de limiar desenvolvido por Martino et al. foram definidos os valores de VGB. A tecnologia referência possui 6 nm de camada de silício (tSi) e no óxido de porta uma camada de 5 nm de SiO2. A segunda tecnologia tem um tSi maior (14 nm) em relação a referência e a terceira tecnologia tem no óxido de porta um material de alta constante dielétrica, HfSiO. Na tecnologia de referência, os dispositivos com GP mostraram melhores resultados para transcondutância na região de saturação (gmSAT) devido ao forte acoplamento eletrostático entre a região da porta e do substrato. Porém os dispositivos com GP apresentam uma maior influência do campo elétrico longitudinal do dreno no canal, assim os parâmetros condutância de saída (gD) e tensão Early (VEA) são degradados, consequentemente o ganho de tensão intrínseco (AV) também. Na tecnologia com tSi de 14 nm, a influência do acoplamento eletrostático entre porta e substrato é menor em relação a referência, devido à maior espessura de tSi. Como a penetração do campo elétrico do dreno é maior em dispositivos com GP, todos os parâmetros analógicos estudados são degradados em dispositivos com GP. A última tecnologia estudada, não apresenta grande variação nos resultados quando comparadodispositivos com e sem GP. O AV, por exemplo, tem uma variação entre 1% e 3% comparando os dispositivos com e sem GP. Foram feitas análises em dispositivos das três tecnologias com comprimento de canal de 70 nm, e todos os parâmetros degradaram com a diminuição do comprimento de canal, como esperado. O fato de ter um comprimento de canal menor faz com que a influência do campo elétrico longitudinal do dreno seja mais relevante, degradando assim todos os parâmetros analógicos nos dispositivos com GP. Nos dispositivos ?G NW SOI MOSFET foram feitas análises em dispositivos pMOS e nMOS com diferentes larguras de canal (WNW = 220 nm, 40 nm e 10 nm) para diferentes VGB. Através de simulações viu-se que dispositivos com largura de canal de 40 nm possuem uma condução de corrente pela segunda interface para polarizações muito altas (VGB = +20 V para nMOS e VGB -20 V para pMOS). Todavia essa condução de corrente na segunda interface ocorre ao mesmo tempo que na primeira interface, impossibilitando fazer a separação dos efeitos de cada interface.A medida que a polarização no substrato faz com que haja uma condução na segunda interface, todos os parâmetros degradam devido a essa condução parasitária. Dispositivos estreitos sofrem menor influência de VGB e, portanto, tem os parâmetros menos degradados, diferente dos dispositivos largos que tem uma grande influência de VGB no comportamento elétrico do transistor. Quando a polarização no substrato é feita a fim de que não haja condução na segunda interface, a variação da inclinação de sublimiar entre dispositivos com WNW = 220 nm e 10 nm é menor que 2 mV/déc. Porém a corrente de dreno de estado ligado do transistor (ION) apresenta melhores resultados em dispositivos largos chegando a 6 vezes maior para nMOS e 4 vezes maior para pMOS que em dispositivos estreitos. Os parâmetros analógicos sofrem pouca influência da variação de VGB. Os dispositivos estreitos (WNW = 10 nm) praticamente têm resultados constantes para gmSAT, VEA e AV. Já os dispositivos largos (WNW = 220 nm) possuem uma pequena degradação de gmSAT para os nMOS, o que degrada levemente o AV em cerca de 10 dB. A eficiência do transistor (gm/ID) apresentou grande variação com a variação de VGB, piorando-a a medida que a segunda interface ia do estado de não condução para o estado de condução. Porém analisando os dados para a tensão que não há condução na segunda interface observou-se que, em inversão forte, a eficiência do transistor apresentou uma variação de 1,1 V-1 entre dispositivos largos (WNW = 220 nm) e estreitos (WNW = 10 nm). Com o aumento do comprimento do canal, esse valor de variação tende a diminuir e dispositivos largos passam a ser uma alternativa válida para aplicação nessa região de operação. / This work aims to study the behavior of the ultrathin body and buried oxide SOI nMOSFET (UTBB SOI nMOSFET) and the horizontal ?-gate nanowire SOI MOSFET (?G NW SOI MOSFET) with the variation of the back gate bias (VGB). The analysis were made through experimental measures and numerical simulation. In the UTBB SOI nMOSFET devices, devices with and without ground plane (GP) implantation of three different technologies were studied. Based on analytical model developed by Martino et al. the values VGB were defined. The reference technology has silicon film thickness (tSi) of 6 nm and 5 nm of SiO2 in the front oxide. The second technology has a thicker tSi of 14 nm comparing to the reference and the third technology has a high-? material in the front oxide, HfSiO. In the reference technology, the devices with GP shows better result for transconductance on saturation region (gmSAT) due to the strong coupling between front gate and substrate. However, devices with GP have major influence of the drain electrical field penetration, then the output conductance (gD) and Early voltage (VEA) are degraded, consequently the intrinsic voltage gain (AV) as well. In the technology with tSi of 14 nm, the influence of the coupling between front gate and substrate is lower because of the thicker tSi. Once the drain electrical field penetration is higher in devices with GP, all analog parameters are degraded in devices with GP. The third technology, presents results very close between devices with and without GP. The AV has a variation from 1% to 3% comparing devices with and withoutGP. Devices with channel length of 70 nm were analyzed and all parameters degraded with the decrease of the channel length, as expected. Due to the shorter channel length, the influence of the drain electrical field penetration is more relevant, degrading all the analog parameters in devices with GP. In the ?G NW SOI MOSFET devices, the analysis were done in nMOS and pMOS devices with different channel width (WNW = 220 nm, 40 nm and 10 nm) for different VGB. By the simulations, devices with channel width of 40 nm have a conduction though the back interface for very high biases (+20 V for nMOS and -20 V for pMOS). However, this conduction occurs at the same time as in the front interface, so it is not possible to separate de effects of each interface. As the substrate bias voltage induces a back gate current, all the parameters are degraded due to this parasitic current. Narrow devices are less affected by VGB and thus its parameters are less degraded, different from wider devices, in which VGB has a greater influence on their behavior. When the back gate is biased in order to avoid the conduction in back interface, the subthreshold swing variation between devices with WNW = 220 nm and 10 nm is lower than 2 mV/déc. However, the on state current (ION) has better results in wide devices reaching 6 times bigger for nMOS and 4 times bigger for pMOS The analog parameterssuffer little influence of the back gate bias variation. The narrow devices (WNW = 10 nm) have practically constant results gmSAT, VEA and AV. On the other hand, wide devices (WNW = 220 nm) have a small degradation in the gmSAT for nMOS, which slightly degrades de AV. The transistor efficiency showed great variation with the back gate bias variation, worsening as the back interface went from non-conduction state to conduction state. However, when the back gate is biased avoiding the conduction in back interface, the transistor efficiency for strong inversion region has a small variation of 1,1 V-1 between wide (WNW = 220 nm) and narrow (WNW = 10 nm) devices. As the channel length increases, this value of variation tends to decrease and wide devices become a valid alternative for applications in this region of operation.