Com a evolução tecnológica há nos dias de hoje um aumento de dispositivos eletrônicos presentes ao nosso redor. Com o passar dos anos diversas funcionalidades vêm sendo agregadas a estes inclusive com maior poder de processamento. Em particular, para sistemas embarcados houve um crescimento da quantidade de sensores para diversos propósitos. Seguindo esta tendência, na área de saúde também houve um aumento significativo de aparelhos e dispositivos de monitoramento, tais como glicosimetros, oxímetros, monitoramento de pressão e batimento cardíaco por exemplo, que através de sensores realizam transdução dos dados pertinentes ao parâmetro envolvido. Este trabalho apresenta a pesquisa e o desenvolvimento de um sistema embarcado com a propriedade de multiplexação de sensores, ou seja, foi desenvolvido um dispositivo microcontrolado o qual visa multiplicar a capacidade de monitoramento de analitos, conseguindo analisar múltiplos sensores para um mesmo experimento. Ao decorrer deste desenvolvimento foram utilizados quatro sensores dispostos simetricamente em um béquer, os dados são coletados e tratados de forma sequencial e individual. Inicialmente utilizamos um sistema embarcado com um microcontrolador (PIC 18F2550) que é responsável por digitalizar a informação e pela conexão via terminal USB. Posteriormente um microprocessador (Raspberry Pi Zero, placa embarcada) fez-se necessário devido ao melhor processamento de dados. Os sensores aqui estudados tratam-se de sensores químicos, que são introduzidos a uma célula eletroquímica, onde se encontram um eletrodo de referência (Prata em uma solução de Cloreto de Prata) e os outros quatro filmes finos que irão compor o sistema multiplexado. Para este estudo em específico o material escolhido para fabricação dos filmes finos foi um polímero condutivo, mais especificamente polianilina (PANI). Esta foi depositada sobre um substrato de oxido de estanho dopado com flúor (FTO) através da eletrodeposição. Para sensores não específicos (não imobilizados para um analito alvo) os dois sistemas embarcados apresentaram respostas satisfatórias. Prosseguindo com o estudo e usando filmes finos para analitos biológicos (ureia e glicose) o microcontrolador não conseguiu separar os sinais de cada filme fino. Apenas o sistema com a Raspberry Pi obteve sucesso, devido a maior resolução no conversor analógico para digital e sua maior capacidade de processamento para determinar com uma maior precisão os valores obtidos. O sistema pode ser facilmente expandido para um maior número de sensores. / With the evolution of technology there is nowadays an increase in the number of electronic devices present around us. Over the years various functionalities have been added to these devices including the increased processing power. In particular, for embedded systems there has been an increase in the number of sensors for various purposes. Following this trend, in the area of health, there has also been a significant increase in systems and monitoring devices, such as glycosimeters, oximeters, pressure monitoring and heart rate, for example, which, through sensors, transduce data pertinent to the parameter involved. This work presents the research and development of an embedded system with the property of multiplexing sensors, that is, a microcontrolled device was developed which aims to multiply the capacity of analytes monitoring, being able to analyze multiple sensors for the same experiment. During this development four sensors were used symmetrically arranged in a beaker, the data were collected and treated sequentially and individually. Initially we used an embedded system with a microcontroller (PIC 18F2550) that is responsible for scanning the information and for the connection via USB terminal. Subsequently a microprocessor (Raspberry Pi Zero, embedded board) was made necessary due to the better processing of data. The sensors studied here are chemical sensors, which are introduced to an electrochemical cell, where a reference electrode is found (Silver in a Silver Chloride solution) and the other four thin films that will make up the multiplexed system. For this specific study the material chosen for the manufacture of thin films was a conductive polymer, more specifically polyaniline (PANI). This was deposited on a substrate of fluorine-doped tin oxide (FTO) by electrodeposition. For non-specific sensors (not immobilized for a target analyte) the two embedded systems presented satisfactory responses. Proceeding with the study and using thin films for biological analytes (urea and glucose) the microcontroller failed to separate the signals from each thin film. Only the system with Raspberry Pi has been successful, due to the higher resolution in the analog to digital converter and its greater processing capacity to determine with greater precision the obtained values. The system can be easily expanded to a larger number of sensors.

Cette thèse expose nos travaux de certification d'une partie d'un programme C/C++ nommé SimSoC (Simulation of System on Chip), qui simule le comportement d'architectures basées sur des processeurs tels que ARM, PowerPC, MIPS ou SH4. Un simulateur de System on Chip peut être utilisé pour developper le logiciel d'un système embarqué spécifique, afin de raccourcir les phases des développement et de test, en particulier quand la vitesse de simulation est réaliste (environ 100 millions d'instructions par seconde par cœur dans le cas de SimSoC). Les réductions de temps et de coût de développement obtenues se traduisent par des cycles de conception interactifs et rapides, en évitant la lourdeur d'un système de développement matériel. SimSoC est un logiciel complexe, comprenant environ 60 000 de C++, intégrant des parties écrites en SystemC et des optimisations non triviales pour atteindre une grande vitesse de simulation. La partie de SimSoC dédiée au processeur ARM, l'un des plus répandus dans le domaine des SoC, transcrit les informations contenus dans un manuel épais de plus de 1000 pages. Les erreurs sont inévitables à ce niveau de complexité, et certaines sont passées au travers des tests intensifs effectués sur la version précédente de SimSoC pour l'ARMv5, qui réussissait tout de même à simuler l'amorçage complet de linux. Un problème critique se pose alors : le simulateur simule-t-il effectivement le matériel réel ? Pour apporter des éléments de réponse positifs à cette question, notre travail vise à prouver la correction d'une partie significative de SimSoC, de sorte à augmenter la confiance de l'utilisateur en ce similateur notamment pour des systèmes critiques. Nous avons concentré nos efforts sur un composant particulièrement sensible de SimSoC : le simulateur du jeu d'instructions de l'ARMv6, faisant partie de la version actuelle de SimSoC. Les approches basées sur une sémantique axiomatique (logique de Hoare par ex- emple) sont les plus répandues en preuve de programmes impératifs. Cependant, nous avons préféré essayer une approche moins classique mais plus directe, basée sur la sémantique opérationnelle de C : cela était rendu possible en théorie depuis la formalisation en Coq d'une telle sémantique au sein du projet CompCert et mettait à notre disposition toute la puissance de Coq pour gérer la complexitité de la spécification. À notre connaissance, au delà de la certification d'un simulateur, il s'agit de la première expérience de preuve de correction de programmes C à cette échelle basée sur la sémantique opérationnelle. Nous définissons une représentation du jeu d'instruction ARM et de ses modes d'adressage formalisée en Coq, grâce à un générateur automatique prenant en entrée le pseudo-code des instructions issu du manuel de référence ARM. Nous générons également l'arbre syntaxique abstrait CompCert du code C simulant les mêmes instructions au sein de Simlight, une version allégée de SimSoC. À partir de ces deux représentations Coq, nous pouvons énoncer et démontrer la correction de Simlight, en nous appuyant sur la sémantique opérationnelle définie dans CompCert. Cette méthodologie a été appliquée à au moins une instruction de chaque catégorie du jeu d'instruction de l'ARM. Au passage, nous avons amélioré la technologie disponible en Coq pour effectuer des inversions, une forme de raisonnement utilisée intensivement dans ce type de situation. / Approaches based on axiomatic semantics (typically, Hoare logic) are the mostpopular for proving the correctness of imperative programs. However, we prefered totry a less usual but more direct approach, based on operational semantics : this wasmade possible in theory since the development of an operational semantics for theC language formalized in Coq in the CompCert project, and allowed us to use thecomfortable logic of Coq, of much help for managing the complexity of the specification.Up to our knowledge, this is the first development of formal correctness proofs basedon operational semantics, at least at this scale.We provide a formalized representation of the ARM instruction set and addressingmodes in Coq, using an automatic code generator from the instruction pseudo-code inthe ARM reference manual. We also generate a Coq representation of a correspondingsimulator in C, called Simlight, using the abstract syntax defined in CompCert.From these two Coq representations, we can then state and prove the correctnessof Simlight, using the operational semantics of C provided by CompCert. Currently,proofs are available for at least one instruction in each category of the ARM instructionset.During this work, we improved the technology available in Coq for performinginversions, a kind of proof steps which heavily occurs in our setting.

nÃo hà / Em projetos de desenvolvimento de sistemas embarcados normalmente adota-se uma abordagem de âtentativa e erroâ nas atividades relacionadas ao porte do sistema operacional(SO), resultando em um porte incompleto ou inconsistente. Nesta pesquisa apresenta-se um trabalho original onde se propÃe uma soluÃÃo para esta abordagem atravÃs de uma metodologia completa para a detecÃÃo das partes do SO que devem ser ajustadas de forma que o SO seja portado para a nova plataforma de hardware. A metodologia proposta combina as informaÃÃes do cÃdigo-fonte do SO e as particularidades do novo hardware, resultando em: uma lista completa do cÃdigo-fonte que deve ser ajustado; a interdependÃncia entre estes cÃdigos-fonte; a ordem de prioridade de modificaÃÃo para cada cÃdigo-fonte; e um cronograma baseado em esforÃo, para auxiliar o planejamento das modificaÃÃes. Adicionalmente, propÃe-se um algoritmo para a resoluÃÃo de referÃncias cÃclicas em arquivos de cÃdigo-fonte. Por fim, à apresentado um estudo de caso baseado em uma aplicaÃÃo desenvolvida segundo a metodologia proposta. / Embedded system development frequently uses the âtrial and errorâ approach for Operating System (OS) porting,resulting in incomplete or inconsistent porting. In this work, we present a pioneer work addressing this issue. We propose a complete method for detecting OS parts that should be adjusted in order to port the OS into a new hardware platform. The proposed method combines information from the OS source-code and peculiarities of the new hardware platform, resulting in: a complete list of source-codes that must be adjusted; the interdependence between these source-codes; the priority order of modifications for each source-code; and an effort-based schedule to help planning the modifications. In addition, we propose an algorithm dealing with source-codeâs cyclic references. Finally, we present a study-case based on an application developed according the proposed method

L'Internet des objets (IoT : Internet-of-Things) a été favorisé par les progrès accélérés dans les technologies de communication, les technologies de calcul, les technologies de capteurs, l'intelligence artificielle, l'informatique en nuage et les technologies des semi-conducteurs. En générale, l'IoT utilise l'informatique en nuage pour traitant les données, l'infrastructure de communication (y compris l’Internet) et des nœuds de capteurs pour collecter des données, de les envoyer de l'infrastructure du réseau à l’Internet, et de recevoir des commandes pour réagir à l'environnement. Au cours de ses opérations, l'IoT peut collecter, transmettre et traiter des données secrètes ou privées, ce qui pose des problèmes de sécurité. La mise en œuvre des mécanismes de sécurité pour l'IoT est un défi, car les organisations de l’IoT incluent des millions de périphériques intégrés à plusieurs couches, chaque couche ayant des capacités de calcul et des exigences de sécurité différentes. En outre, les nœuds de capteurs dans l'IoT sont conçus pour être des périphériques limités par une batterie, avec un budget de puissance, des calculs et une empreinte mémoires limités pour réduire les coûts d’implémentation. L'implémentation de mécanismes de sécurité sur ces appareils rencontre même plus de défis. Ce travail est donc motivé pour se concentrer sur l’implémentation du cryptage des données afin de protéger les nœuds et les systèmes de capteurs IoT en tenant compte du coût matériel, du débit et de la consommation d’énergie. Pour commencer, un crypto-accélérateur de chiffrement de bloc ultra-basse consommation avec des paramètres configurables est proposé et implémenté dans la technologie FDSOI ST 28 nm dans une puce de test, qui est appelée SNACk, avec deux modules de cryptographie : AES et PRESENT. L’AES est un algorithme de cryptage de données largement utilisé pour l’Internet et utilisé actuellement pour les nouvelles propositions IoT, tandis que le PRESENT est un algorithme plus léger offrant un niveau de sécurité réduit mais nécessitant une zone matérielle beaucoup plus réduite et une consommation très bas. Le module AES est une architecture de chemin de données 32 bits contenant plusieurs stratégies d'optimisation prenant en charge plusieurs niveaux de sécurité, allant des clés 128 bits aux clés 256 bits. Le module PRESENT contient une architecture à base arrondie de 64 bits pour optimiser son débit. Les résultats mesurés pendant cette thèse indiquent que ce crypto-accélérateur peut fournir un débit moyen (environ 20 Mbits/s au 10 MHz) tout en consommant moins de 20 µW dans des conditions normales et une sous-pJ d’énergie par bit. Cependant, la limitation du crypto-accélérateur réside dans le fait que les données doivent être lues dans le crypto-accélérateur et réécrites en mémoire, ce qui augmente la consommation d'énergie. Après cela, afin de fournir un haut niveau de sécurité avec une flexibilité et une possibilité de configuration pour s’adapter aux nouvelles normes et pour atténuer les nouvelles attaques, ces travaux portent sur une approche novatrice de mise en œuvre de l’algorithme de cryptographie utilisant la nouvelle SRAM proposée en mémoire. Le calcul en mémoire SRAM peut fournir des solutions reconfigurables pour mettre en œuvre diverses primitives de sécurité en programmant les opérations de la mémoire. Le schéma proposé consiste à effectuer le chiffrement dans la mémoire en utilisant la technologie Calcul en Mémoire (In-Memory-Computing). Ce travail illustre deux mappages possibles de l'AES et du PRESENT à l'aide du calcul en mémoire. / The Internet of Things (IoT) has been fostered by accelerated advancements in communication technologies, computation technologies,sensor technologies, artificial intelligence, cloud computing, and semiconductor technologies. In general, IoT contains cloud computing to do data processing, communication infrastructure including the Internet, and sensor nodes which can collect data, send them through the network infrastructure to the Internet, and receive controls to react to the environment. During its operations, IoT may collect, transmit and process secret data, which raise security problems. Implementing security mechanisms for IoT is challenging because IoT organizations include millions of devices integrated at multiple layers, whereas each layer has different computation capabilities and security requirements. Furthermore, sensor nodes in IoT are intended to be battery-based constrained devices with limited power budget, limited computation, and limited memory footprint to reduce costs. Implementing security mechanisms on these devices even encounters more challenges. This work is therefore motivated to focus on implementing data encryption to protect IoT sensor nodes and systems with the consideration of hardware cost, throughput and power/energy consumption. To begin with, a ultra-low-power block cipher crypto-accelerator with configurable parameters is proposed and implemented in ST 28nm FDSOI technology in SNACk test chip with two cryptography modules: AES and PRESENT. AES is a widely used data encryption algorithm for the Internet and currently used for new IoT proposals, while PRESENT is a lightweight algorithm which comes up with reduced security level but requires with much smaller hardware area and lower consumption. The AES module is a 32-bit datapath architecture containing multiple optimization strategies supporting multiple security levels from 128-bit keys up to 256-bit keys. The PRESENT module contains a 64-bit round-based architecture to maximize its throughput. The measured results indicate that this crypto-accelerator can provide medium throughput (around 20Mbps at 10MHz) while consumes less than 20uW at normal condition and sub-pJ of energy per bit. However, the limitation of crypto-accelerator is that the data has to be read into the crypto-accelerator and write back to memory which increases the power consumption. After that, to provide a high level of security with flexibility and configurability to adapt to new standards and to mitigate to new attacks, this work looks into an innovative approach to implement the cryptography algorithm which uses the new proposed In-Memory-Computing SRAM. In-Memory Computing SRAM can provide reconfigurable solutions to implement various security primitives by programming the memory's operations. The proposed scheme is to carry out the encryption in the memory using the In-Memory-Computing technology. This work demonstrates two possible mapping of AES and PRESENT using In-Memory Computing.

Building Automation System (BAS) is a complex distributed control system that is widely deployed in commercial, residential, industrial buildings for monitoring and controlling mechanical/electrical equipment. Through increasing industrial and technological advances, the control components of BAS are becoming increasingly interconnected. Along with potential benefits, integration also introduces new attack vectors, which tremendous increases safety and security risks in the control system. Historically, BAS lacks security design and relies on physical isolation and "security through obscurity". These methods are unacceptable with the "smart building" technologies. The industry needs to reevaluate the safety and security of the current building automation system, and design a comprehensive solution to provide integrity, reliability, and confidentiality on both system and network levels. This dissertation focuses on the system level in the effort to provide a reliable computing foundation for the devices and controllers. Leveraged on the preferred security features such as, robust modular design, small privilege code, and formal verifiability of microkernel architecture, this work describes a security enhanced operating system with built-in mandatory access control and a proxy-based communication framework for building automation controllers. This solution ensures policy-enforced communication and isolation between critical applications and non-critical applications in a potentially hostile cyber environment.

Progress

<p>The IEEE 802.11b standard is today the only commonly used standard in Europe for fast wireless networks. This makes it possible to connect computers to networks in places where it is not possible to use wires. Examples of such situations are internet access at airports, communication in emergency areas or for military communication. Common for all these situations is that network security is important. </p><p>This thesis consists of two different parts. The first part handles the security mechanisms and the second part is an evaluation of the possibilities to use IEEE 802.11b in embedded applications. The part that handles the security includes the security mechanisms found in the standard, flaws in these mechanisms and methods that try to reduce these problems.</p>

<p>Security issues appearing in one or another form become a requirement for an increasing number of embedded systems. Those systems, which will be used to capture, store, manipulate, and access data with a sensitive nature, have posed several unique and urgent challenges. The challenges to those embedded system require new approaches to security covering all aspects of embedded system design from architecture, implementation to the methodology. However, security is always treated by embedded system designer as the addition of features, such as specific cryptographic algorithm or other security protocol. This paper is intended to draw both the SW and HW designer attention to treat the security issues as a new mainstream during the design of embedded system. We intend to show why hardware option issues have been taken into consideration and how those hardware mechanisms and key features of processor architecture could be implemented in the hardware level (through modification of processor architecture, for example) to deal with various potential attacks unique to embedded systems.</p>

With continuous advancement in silicon technology and high feature demands on consumer electronics, the complexity of embedded software has led the software development effort to dominate System-On-Chip (SoC) design. Virtual Prototype (VP) addresses the problem by enabling early software development before hardware arrival. However, VP still poses challenges: 1) Instruction Set Simulator (ISS) degrades simulation time, 2) Development is restricted to embedded processor specific tools and 3) Applications and drivers are dependent on system software completion. In this work, we propose an abstraction framework which: 1) Removes ISS from VP, achieving native host software execution time, 2) Activates rich suites of desktop development tools in host by compiling embedded software in host binary and 3) Allows system software independent application and driver development. With this framework, we successfully demonstrated up to 2000% speed-up in VP run-time over conventional VP and improved software development productivity significantly.

With continuous advancement in silicon technology and high feature demands on consumer electronics, the complexity of embedded software has led the software development effort to dominate System-On-Chip (SoC) design. Virtual Prototype (VP) addresses the problem by enabling early software development before hardware arrival. However, VP still poses challenges: 1) Instruction Set Simulator (ISS) degrades simulation time, 2) Development is restricted to embedded processor specific tools and 3) Applications and drivers are dependent on system software completion. In this work, we propose an abstraction framework which: 1) Removes ISS from VP, achieving native host software execution time, 2) Activates rich suites of desktop development tools in host by compiling embedded software in host binary and 3) Allows system software independent application and driver development. With this framework, we successfully demonstrated up to 2000% speed-up in VP run-time over conventional VP and improved software development productivity significantly.