Video streaming has become increasingly popular with commercial video streaming applications such as YouTube accounting for a large quantity of Internet traffic. While streaming video is sensitive to bandwidth jitter, a receiver buffer can ameliorate the effects of jitter by adjusting to the difference between the transmission rate and the playback rate. Unfortunately, there are few studies to determine the best size of the receiver buffer for TCP streaming. In this work, we investigate how the buffer size of video streaming applications changes with respect to variation in bandwidth. We model the video streaming system over TCP using simulation to develop our buffering algorithm. We propose using a dynamic client buffer size based on measured bandwidth variation to achieve fewer interruptions in video streaming playback. To evaluate our approach, we implement an application to run experiments comparing our algorithm with the buffer size of commercial video streaming.

<p>As intrusion attacks on systems become more and more complex, the tools trying to stop these attacks must follow. This thesis has developed a testbed to test and evaluated three freely available protection tools for the GNU/Linux platform to see how they fare against attacks.</p>

Self-Determination Theory (SDT) research on goal pursuit indicates that people with intrinsic goal pursuits experience greater well-being than those with extrinsic goal pursuits. Three nutriments have been suggested by SDT that facilitate intrinsic motivation: autonomy, competence and relatedness. These nutriments, considered social conditions by SDT, have been understudied. However, recent SDT research and the small literature on goal support in relationships suggest that social aspects of goal pursuit are quite relevant and warrant further investigation. This study examined interpersonal dimensions of goal pursuit including Goal Support, Shared Goals, Communal Strength and Generativity. This interpersonal cluster was examined in the context of "active involvement with others" in order to enrich our understanding of the link between goal pursuit and psychological well-being. This study was the first to explore these interpersonal dimensions of goal pursuit and well-being in the context of SDT. Correlations explored the relationships among the interpersonal dimensions and regression analyses were used to explore moderating effects the interpersonal dimensions had on the relationship between self-concordant (intrinsic/extrinsic) goal pursuit and well-being. Shared goal orientation was the only dimension to act as a moderator. Implications include continuing to identify the active role of others in one's goal pursuits and adding further understanding to the relationship between goal pursuit and well-being.

In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in determining circuit performance including timing, power consumption, cost, power supply noise and tolerance to process variations. It is required that a clock layout algorithm can achieve any prescribed skews with the minimum wire length and acceptable slew rate. Traditional zero-skew clock routing methods are not adequate to address this demand, since they tend to yield excessive wire length for prescribed skew targets. The interactions among skew targets, sink location proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and buffer area, which results in lesser cost, power consumption and vulnerability to process variations. During the clock routing, buffers are inserted simultaneously to facilitate a proper slew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that the algorithm can reduce the total wire and buffer capacitance by 60% over an extension of the existing zero-skew routing method.

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay.

In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in determining circuit performance including timing, power consumption, cost, power supply noise and tolerance to process variations. It is required that a clock layout algorithm can achieve any prescribed skews with the minimum wire length and acceptable slew rate. Traditional zero-skew clock routing methods are not adequate to address this demand, since they tend to yield excessive wire length for prescribed skew targets. The interactions among skew targets, sink location proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and bu&#64256;er area, which results in lesser cost, power consumption and vulnerability to process variations. During the clock routing, bu&#64256;ers are inserted simultaneously to facilitate a proper slew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that the algorithm can reduce the total wire and bu&#64256;er capacitance by 60% over an extension of the existing zero-skew routing method.

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay.

The thesis is composed of two topics : a fully bidirectional mixed-voltage-tolerant I/O buffer using a clamping dynamic gate bias generator and a wide range fully bidirectional mixed-voltage-tolerant I/O buffer with a calibration function. The first topic, a mixed-voltage-tolerant I/O buffer implemented in 2P4M 0.35 £gm CMOS process, comprises a low-power bias circuit with clamping transistors in a feedback loop, a power supply level detector circuit, a voltage level converter circuit, a logic switch circuit, a dynamic driving detector circuit, and a clamping dynamic gate bias generator. The proposed design can transmit and receive digital signals with voltage levels of 5/3.3/1.8 V without any gate-oxide overstress and leakage current path in different voltage interface applications. The second topic, a 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage-tolerant I/O buffer carried out in 2P4M 0.35 £gm CMOS technology, contains a dynamic gate bias generator to provide appropri¬ate gate voltages for the output stage composed of stacked PMOS and stacked NMOS, an I/O buffer which can transmit the signal with a higher voltage level (VDDH), a floating N-well circuit to remove the body effect at the output PMOS, and a dynamic driving detector to balance the turn-on voltages for the pull-up PMOS and pull-down NMOS in the output stage. The duty cycle of the output signal of the proposed I/O buffer can then be equalized even if the output stage power supply is biased at a low voltage. In order to adapt to wide range input voltage applications, a logic calibration circuit is added in the input buffer.

The coastal planning has been developed in purpose of the ¡§safely¡¨, ¡§landscaping¡¨, ¡§ecology¡¨ and ¡§water affinity¡¨ in Taiwan nowadays. Moreover, the hendland bay beachs and beach nourishment have been hailed for the protection of shoreline. One of the main affection of erosion is a storm, which retreads shoreline and reduces nearshore by storm surge. This essay reports an application of 2-D SBEACH software to simulate the beach profile changes. The data of large wave tank (LWT), which tests by the Coastal Engineering Research Center (CERC), US Army Corps of Engineers, is used to calibrate the parameters by SBEACH. Then, using the results of experimentation to indicate the accuracy of model from Grosser Wellen Kanal (GWK), which tests by the University of Hannor. Finally, simulating beach profile, with a berm (height of 2.5m and width of 100m) and a slope of 1:25, is used to simulate the profile changes and analyze the results by different storm conditions from CECI. The purpose of this paper is to estimate the suitable distance of shoreline and location of bar for a beach buffer zone by SBEACH during different storm conditions. The present study confirms that the simulated results of shoreline erosion rate and the position of bar crest by SBEACH comform to the LWT and GWK experiments. The major parameters of SBEACH, the transport rate coefficient, K influences the sediment transport, coefficient for slope-dependent term, £` controls the slope of beach profile and shape of bar, the transport rate decay coefficient multiplier, Kb affects the shoreline erosion, and the landward surf zone depth, db influences the shape of berm. The result of analysis by SBEACH indicates that a constant slope beach profile changes by different storm conditions and the extent of non-dimensional shoreline retreat Xt/Lo is found in good linear relationship with deepwater wave steepness Ho/Lo. Therefore, the linear regress function is used to compute the less beach buffer zone in different storm conditions.

Because the past researches of the North Korea¡¦s nuclear problem are devoid of a classical geopolitics approach, this article will explain this problem from the traditional ¡§buffer state¡¨ approach. Nuclear weapons symbolize absolute attack ability. Because of many limitations superpowers cannot smoothly transform nuclear weapons to a deterrence function; however, small countries have advantages that superpowers do not possess in using nuclear weapons so they can break these limitations and favorably transform nuclear weapons to a deterrence function. North Korea can take these advantages to change the fate of geopolitics in the past, which was a weak buffer state, and use nuclear weapons to stabilize the whole buffer system to achieve the goal of extending the peacetime. Thus, North Korea's very effort to obtain nuclear weapons is the process of stabilizing the buffer system but this does not mean that North Korea can sit without worries. The problem of the successor and the economic breakdown are two Achilles' heels in North Korea, both of which have the risk that will destroy the whole buffer system.