As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory - STT MRAM (Spin-Torque Transfer Magnetic RAM) which provides substantial power and area savings, near zero leakage power, and displays higher memory density compared to conventional SRAM. But STT-MRAM suffers from inherit drawbacks like multi cycle write latency and high write power consumption. So, these problem have to addressed in order to have an efficient design to incorporate STT-MRAM for NoC input buffer instead of traditional SRAM based input buffer design. Motivated by short intra-router latency, previously proposed write latency reduction technique is explored by sacrificing retention time and a hybrid design of input buffers using both SRAM and STT-MRAM to "hide" the long write latency efficiently is proposed. Considering that simple data migration in the hybrid buffer consumes more dynamic power compared to SRAM, a lazy migration scheme that reduces the dynamic power consumption of the hybrid buffer is also proposed.

Thesis--Auburn University, 2008. / Abstract. Includes bibliographical references (p. 52-56).

Thesis (M. Phil.)--University of Hong Kong, 1989.

No description available.

A Buffer management algorithm plays an important role in determining the packet loss ratio in a computer network. Two types of packet buffer management algorithms, static and dynamic, can be used in a Network Interface Card (NIC) of a network terminal. In general, dynamic algorithms have better efficiency than the static algorithms. However, once the allocated buffer space is filled for an application, further incoming packets for that application get rejected. We propose a history-based scheme called History Based Dynamic Algorithm (HBDA), which reduces packet loss ratio by monitoring whether or not the application is active. For average network traffic loads, the HBDA improves the packet loss ratio by 15.9% and 11% (for load = 0.7) compared to DA and DADT, respectively. For heavy traffic load, improvement is 16.2% and 11.7% (for load = 0.7) and for actual traffic load improvement is 12.7% and 7.1% (for load = 0.7) over DA and DADT respectively. We also developed a new architecture for the Network Interface Card. The new architecture will support the multi-processor system and gives more consideration to the application with the highest priority. It has two control units for processing the incoming packets in parallel. For the traffic mix with average network traffic loads , the new architecture improves the packet loss ratio for priority application by a significant amount.

Generally, dielectrophoresis (DEP) analysis of biological cell samples relies on the differing electrical parameters between the cells and the surrounding fluid medium. To achieve effective positive DEP manipulation and sorting of mammalian cells in suspension, it is required to resuspend the cells into a low-conductivity fluid buffer. The use of a low conductivity buffer also aids in minimizing the effects of Joule heating, which can cause cell death and ineffective cell trapping. The common method to prepare the sample relies on centrifugation of sensitive cells, a time-consuming and tedious process that may result in decreased sample viability. Herein is presented a microfluidic device that passively moves cells from a high-conductivity growth media into a low-conductivity DEP buffer. It is comprised of con- verging rows of pillars and uses mechanical filtration to force cells into the new buffer while allowing for the old fluid to flow through the posts and out of separate outlets. Because this device is intended to be used upstream of a contactless dielectrophoresis (cDEP) device, the buffer exchange device must have an outlet flow rate that is within the range necessary for direct integration with the cDEP device, maintain a low shear stress that will not affect the integrity of the sample and achieve sufficiently high cell recovery. Methods of this project included optimizing the shape, size, and orientation of the posts, determining the flow rate for maintaining an ideal DEP buffer conductivity, numerical modeling of shear stress, and determining the cell recovery rate. It is anticipated that this device can be extended to physiological media sample processing such as for liquid biopsy. / Master of Science / In order to accomplish numerous biomedical experiments, cells must be transferred from their native fluid growth media into a different fluid solution, through a process referred to as buffer exchange. The current method for buffer exchange is time consuming, tedious, and affects the number of cells left alive for experimentation. In this work, we present a microfluidic device that can accomplish the buffer exchange process by simply flowing in the cells in their media in parallel with the new buffer solution. The results of this research work can be extended to aid in the process of buffer exchange for various biological experiments. The proposed device utilizes mechanical filtration to force cells into the new buffer while allowing for the old fluid to flow through the posts and out of separate outlets. The design of the device was optimized through computational analysis of the concentration and fluid shear stress in conjunction with experimental tests of devices for outlet conductivity and cell retention.

Buffer pools are blocks of memory used in database systems to retain frequently referenced pages. Configuring the buffer pools is a difficult and manual task that involves determining the amount of memory to devote to the buffer pools, the number of buffer pools to use, their sizes, and the database objects assigned to each buffer pool. A good buffer configuration improves query response times and system throughput by reducing the number of disk accesses. Determining a good buffer configuration requires knowledge of the database workload. Empirical studies have shown that optimizing the initial buffer configuration (determined at database design time) can improve system throughput. A good initial configuration can also provide a faster convergence towards a favorable dynamic buffer allocation. Previous studies have not considered automating the buffer pool configuration process. This thesis presents two techniques that facilitate the initial buffer configuration task. First, we develop an analytic model of the GCLOCK buffer replacement policy that can be used to evaluate the effectiveness of a particular buffer configuration for a given workload. Second, to obtain the necessary model parameters, we propose a workload characterization scheme that extracts workload parameters, describing the query reference patterns, from the query access plans. In addition, we extend an existing multifractal model and present a multifractal skew model to represent query access skew. Our buffer model has been validated against measurements of the buffer manager of a commercial database system. The model has also been compared to an alternative GCLOCK buffer model. Our results show that our proposed model closely predicts the actual physical read rates and recognizes favourable buffer configurations. This work provides a foundation for the development of an automated buffer configuration tool.

Buffer pools are blocks of memory used in database systems to retain frequently referenced pages. Configuring the buffer pools is a difficult and manual task that involves determining the amount of memory to devote to the buffer pools, the number of buffer pools to use, their sizes, and the database objects assigned to each buffer pool. A good buffer configuration improves query response times and system throughput by reducing the number of disk accesses. Determining a good buffer configuration requires knowledge of the database workload. Empirical studies have shown that optimizing the initial buffer configuration (determined at database design time) can improve system throughput. A good initial configuration can also provide a faster convergence towards a favorable dynamic buffer allocation. Previous studies have not considered automating the buffer pool configuration process. This thesis presents two techniques that facilitate the initial buffer configuration task. First, we develop an analytic model of the GCLOCK buffer replacement policy that can be used to evaluate the effectiveness of a particular buffer configuration for a given workload. Second, to obtain the necessary model parameters, we propose a workload characterization scheme that extracts workload parameters, describing the query reference patterns, from the query access plans. In addition, we extend an existing multifractal model and present a multifractal skew model to represent query access skew. Our buffer model has been validated against measurements of the buffer manager of a commercial database system. The model has also been compared to an alternative GCLOCK buffer model. Our results show that our proposed model closely predicts the actual physical read rates and recognizes favourable buffer configurations. This work provides a foundation for the development of an automated buffer configuration tool.

This thesis presents an efficient buffer management scheme for 3-D graphic rendering systems. The purpose of this scheme is to reduce the off-chip memory accesses, which have become a valuable resource, and very often a performance bottleneck of embedded 3-D applications. The 3-D buffers, including depth and color frame buffers, will be divided into rectangular blocks. The proposed scheme can first provide the management of buffer clear operation. For most of time, the rendering of each 3-D frame starts from the buffer clear command to clear the data remaining in buffers from the previous frame. Instead of clearing the buffers residing in the off-chip memory immediately, our scheme will just set the clear flag in an on-chip buffer management table which provides a control information entry for each of the blocks in the buffer. When the blocks have to be accessed later during rendering process, they won¡¦t be brought in from on-chip memory; instead, they are cleared directly in the corresponding cache location. When the cache blocks are replaced, the corresponding off-chip buffer blocks will be updated. Only those blocks in the off-chip color buffer which are not visited will be actually cleared when the color frame is swapped for display. The second contribution of the propose management scheme is to compress and decompress the depth blocks to save the transfer data amount of these blocks. Since the difference of the depth values of the neighboring pixels belonging to the same triangle plane will be the same, this difference value can be stored and encoded along with the run-length information which can lead to significant saving of the storage space. The actual reduction ratio depends on the relative object complexity to the output screen size, the block size, and the degree of the anti-aliasing considered. However, our experimental results show that the compression ratio of 17-28% can be achieved for the moderate block size. The entire buffer management has been implemented, and the entire gate count is 65k, which is about 10% of the entire 3-D systems. The proposed management chip is very suitable for embedded 3D graphic rendering systems where the memory bandwidth budget is very tightly restricted.

No description available.