Las cintas superconductoras de alta temperatura (HTS) han emergido como materiales prometedores para sus uso en el campo de l'energía puesto que permiten reducir a mitad el tamaño de los equipos de energía eléctrica respecto a los convencionales, reducir las pérdidas de energía, aumentar la eficacia en la generación, la transmisión y la distribución de la misma, y así la reducir el impacto ambiental.Sin embargo, diversamente de los conductores típicos, los materiales superconductores basados en óxido son frágiles, se dañado fácilmente y son así difíciles de procesar. Hasta ahora ha sido posible producir longitudes de un kilómetro de cables HTS de primera generación, para el uso en el trasporte de corriente eléctrica. Las cintas superconductoras de YBCO, por ejemplo, pueden soportar altas densidades de corrientes críticas y por esto representan un candidato prometedor en el trasporte de electricidad.Uno del los substratos disponible para suportar el superconductor es un acero policristalino con una película epitaxial de YSZ en cima, YSZ(IBAD)/Stainless. El segundo que hemos utilizado es el NiO(SOE)/Ni(Rabit), una cinta de nickel previamente texturada por laminación y sucesivamente oxidata de manera controlada. Numerosas técnicas están disponible para la deposición de YBCO epitaxiale, nosotros elegimos el proceso más barato y industrialmente interesante: la técnica sol-gel. Para evitar la interacción entre el YBCO superconductor y el substrato epitaxial, evitando así la reducción de la corriente que el superconductor puede trasportar, es importante interponer un material inerte que transfiera su epitaxia al YBCO; este clase de películas se llaman capas tampón. El objetivo principal de esta tesis ha sido optimizar el crecimiento de las capas tampón por técnica química y finalmente estudiar la deposición del YBCO por TFA sobres esas muestras optimizadas. Las capas de cerámica que hemos estudiados han sido: CeO2, BaZrO3, CaZrO3, SrZrO3, SrTiO3, BaCeO3 , y depositadas por el método químico: metal 2-4-&#61538;-diketone disuelto en ácido acético, o los metales isopropoxidos disuelto en metanol. Por depositar las soluciones precursoras hemos utilizado la técnica de spin coating. Controlando los diversos parámetros, velocidad, aceleración y la concentración de la solución obtuvimos películas homogéneas con diverso grosor. La fase de la cristalización se alcanza en un horno donde se controla l'atmósfera, la temperatura y la velocidad de calefacción. Durante esta investigación hemos adquirido un conocimiento total del acrecimiento de las películas delgada de MOD-CeO2. De una combinación de las análisis de TEM, de XRD y de RHEED observamos que el mecanismo de crecimiento tiene un comportamiento anómalo comparado con el otro materiales crecidos con la misma técnica.En este proceso de síntesis de la ceria, la nucleation homogénea de hecho esta favorita debido al bajo valor de Tnuc./Tmel ceria (Tnuc./Tmel=0.21). Solamente los granos nucleados sobre el substrato resultan texturados. La dependencia del tamaño de grano con temperatura sigue una relación de tipo Arrhenius, características de un crecimiento 3D del grano. Los análisis de EELS revelaron una fracción significativa de C residual que adorna los límites de grano, es probable que el crecimiento del límite de grano se quede bloqueando debido estas impurezas.Un proceso del recocido en aire a posteriores, ha demostrado la posibilidad de crecer las películas de CeO2 totalmente epitaxiales. Los análisis de EELS de tales muestras tratadas en oxígeno demuestran claramente que los límites de grano quedan limpios de las impurezas de C, desbloqueando así el crecimiento del grano. Después de un proceso largo de optimización de los parámetros de síntesis, podemos ahora controlar exactamente el crecimiento epitaxiale de la ceria. Se ha verificado que el óxido del cerio se puede crecer en YSZ(IBAD)/SS con solamente la orientación (00l). Para preservar la cinta del metal contra la oxidación, el proceso optimizado se ha adaptado a la deposición sobre substrato de acero inoxidable reduciendo la temperatura de síntesis a 900ºC. Hemos optimizado también la preparación de SrTiO3(STO) y BaZrO3(BZO) sobre MgO y YSZ mono-cristales y en seguida también sobre YSZ(IBAD)/SS y NiO(SOE)/Ni.La arquitectura más prometedora resultó ser STO/BZO/NiO(SOE)/Ni. Por ultimo depositamos YBCO por método TFA (Trifluoracéticetatos) sobre las capas tampones optimizadas. Una muestra de TFA-YBCO sobre CeO2/YSZ(IBAD)/SS preparada en aire a 900ºC en 8 h ha dato como resultado una densidad corriente crítica, Jc de 7 MA/cm2 a 5K, y 6·105A/cm2 a 77K. Estos valores están cerca de objectivo de un millón A/cm2 a 77K. Los experimentos sobre las capas tampón de BZO y de STO han demostrado la posibilidad de usar este sistema doble sobre NiO(SOE)/Ni como plantilla alternativa para el crecimiento de YBCO. Alcanzado una densidad de corriente crítica de Jc(5K) = 5·105A/cm2 con la mejor muestra de YBCO/STO/BZO/NiO(SOE)/Ni. / High-temperature superconducting (HTS) tapes have emerged as promising materials for superconducting power applications since they make possible electric power equipment that is half the size of conventional alternatives, with half energy losses, increasing the efficiency in the generation, transmission and distribution of the electric energy, and thus reducing the impact of power delivery on the environment. However, unlike typical conductors, oxide based superconductor materials are brittle and easily damaged and thus they are difficult to process and handle, specially forming large and flexible wires.Up to now it has been possible to produce kilometre lengths of the first generation of HTS wires for use in electrical transmission cables. YBCO coated conductors can support high critical current densities and is a promising candidate. One of the substrate available is a polycrystalline metal substrate with an epitaxial YSZ film on it, the ion-beam assisted deposition YSZ(IBAD)/Stainless Steel. The second is the textured NiO(SOE)/Ni(Rabit).Numerous methods are available for epitaxial deposition of YBCO, including vacuum techniques but we choose the cheaper non vacuum sol-gel processes.To avoid the interaction between the superconductor it is important to interpose a inert material that can transfer the epitaxy from the substrate to the YBCO, these kind of films are called buffer layers, avoiding than the reduction of the current that the superconductor can support. The main aim of this thesis was optimising the buffer layer growth by chemical technique and finally studying the deposition of TFA-YBCO on those optimised templates.The ceramic buffer layers studied:CeO2 , BaZrO3 , CaZrO3, SrZrO3, SrTiO3,BaCeO3The Sol-Gel system used was the Metal &#61538;-diketone dissolved in Acid Acetic, or Metal isopropoxide dissolved in methanol.The deposition step was performed by spin coating. Controlling the different parameters of rate and acceleration of the spinner and the precursor solution concentration we obtained homogenous films with different thickness. The crystallisation step is achieved in a furnace in a controlled atmosphere, temperature and heating rate.Important knowledge on the MOD-CeO2 thin film growth has been acquired during this research. From a combination of TEM, XRD and RHEED analyses it was observed that its growth mechanism exhibits an anomalous behaviour compared with other CSD derived films. The homogeneous nucleation in fact is favoured in this MOD process due to the low Tnuc./Tmel value for ceria film (Tnuc./Tmel=0.21). Only grains nucleated on the substrate are textured as observed in XTEM images. The grain size dependence with temperature follows an Arrhenius relation: <r>2=&#61537;otexp(-Q/kT), characteristics of 3D undergoing thermally activated grain growth . EELS analyses revealed a significant fraction of residual C decorating the grain boundaries, that very likely acts as a growth by blocking grain boundary motion. A process of post annealing or direct growth in static air, have demonstrated the possibility of growing completely epitaxial CeO2 films. EELS analyses of such samples clearly demonstrates that the oxygen clean up grain boundaries from C impurities thus unblocking grain growth. After a long process of synthesis parameter optimisation, we are now able to control exactly the epitaxial growth of ceria growth. It has been verified that Cerium oxide can be grown on YSZ(IBAD)/SS with only the (00l) orientation. The optimised process has been adapted to stainless steel substrate reducing the synthesis temperature at 900ºC in order to preserve the metal tape against oxidation. We observed an interesting phenomenon of in plane texture improvement of the ceria film with respect to the underlying YSZ(IBAD)/SS substrate, from &#61508;&#61542;YSZ = 8.3º and to &#61508;&#61542;CeO2 = 7.5º.The solution preparation and the deposition conditions for STO and BZO on MgO and YSZ have been also optimised. After several experiments of buffer deposition on YSZ(IBAD)/SS and NiO(SOE)/Ni technical metal substrates the most promising architecture resulted to be the STO/BZO/NiO(SOE)/Ni. We have grown YBCO by the TFA(Trifluor Acetic Acid) method on the optimized buffer layers. A sample of TFA-YBCO on a CeO2/YSZ(IBAD)/SS template prepared in air at 900ºC for 8 h has shown a critical current density, Jc has a value of 7 MA/cm2 at 5K, and 6·105A/cm2 at 77K. These values are near the target of one million A/cm2 at 77K. The experiments on BZO and STO buffer layers have demonstrated the possibility of using the double buffer on NiO(SOE)/Ni as an alternative template for YBCO deposition. A critical current density of Jc(5K)= 5·105A/cm2 has been achieved for the best sample of YBCO/STO/BZO/NiO(SOE)/Ni.

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In todays GSM network more and more interfaces are run over IP instead of classic synchronized networks. This rises new issues to be solved, for example handling of jitter that use of IP networks introduces. The jitter can be handled by a jitter buffer which ensures that the packets are forwarded in evenly spaced intervals. In GSM, data is requested a certain time in advance before delivery to a cellphone. This "time in advance" needs to be adjusted according to the delay of the channel. For an IP network this delay varies (jitter), which means that it would be beneficial to have an algorithm which continuously adjusts how long in advance the packets should be requested. The adjustment is made according to current channel delay and jitter size. In this thesis work a model of a general IP network has been developed and isthen used for development of two algorithms for jitter buffer handling. Once the algorithms have been developed they are evaluated and compared to each other and previous solutions to the problem. One of the algorithms is new and the other is an already existing algorithm that has been extended. The simplified conclusion is that the behaviors of both algorithms are very similar. They mainly have small packet loss but sometimes the packets are requested earlier than needed and therefore are kept in the buffer a bit longer than necessary. When comparing the two developed algorithms with previous solutions it is visible that they improve the buffer handling a great deal.

This thesis experimentally investigates the effects of buffer regulation on the delivery of randomly spaced objects through a multi-conveyor system according to a demanded throughput and spacing. A regulator is developed and tested in conjunction with on ongoing research project at Georgia Tech investigating the automated transfer of live birds. In this thesis, an algorithm is proposed to identify and compensate for the spacing deviations of objects entering a system comprised of three serially connected conveyors. The regulator acts to delay the time each object spends on the middle conveyor, eliminating spacing variations by the time objects exit the system. The system is experimentally tested to determine how effectively the algorithm can locate and deliver objects onto specific moving points. The limits of the regulator and the considerations for practical implementation are investigated. The proposed buffering regulator has immediate applications in the poultry processing industry, wherein live birds must be sorted and hung on a uniform shackle line moving at a constant speed.

When designing analog circuits, we must ultimately perform measurements on the fabricated chips to determine whether they work correctly or not. The test results are compared with simulation results to determine what the differences to the expected results are. Therefore, incremental improvement and redesign becomes possible. We can obtain highly important information from the test results, making circuit testing a very important aspect of the process of analog circuit design. Especially, measurements during the development phase may include internal circuit nodes which will not be accessible in a final design but are pinned out specifically in the development phase. Because the probing tools present capacitive loads to the circuit, these additional loads may affect the analog circuits‟ response, especially in a high frequency range. Therefore, decreasing influence of capacitive loads of the probing tools in the testing environment is very important. We use analog buffers to separate the analog circuit node from the probing tools. Therefore, the buffer becomes a very important block in analog circuit testing [1-3]. For adapting to different testing environments, this thesis examines three different types of buffer which are designed using a partially modular method [4, 5]. All buffers provide a DC to 1 MHz bandwidth. The first buffer module provides a -1.3 V~1.3 V signal range driving 25 pf~85 pf capacitive loads; the second buffer has a -0.8 V~0.8 V range with for 5 pf~25 pf loads; the third buffer yields -0.5 V~0.5 V range with 1 pf~5 pf loads. The circuit design is discussed and simulated results are presented. Finally, measured results are reported for an open-loop output stage with near unity gain (buffer three). This circuit was previously fabricated in 0.35 £gm CMOS technology.

The scaling of VLSI technology has spurred a rapid growth in the semiconductor industry. With the CMOS device dimension scaling to and beyond 90nm technology, it is possible to achieve higher performance and to pack more complex functionalities on a single chip. However, the scaling trend has introduced drastic variation of process and design parameters, leading to severe variability of chip performance in nanometer regime. Also, the manufacturing community projects CMOS will scale for three to four more generations. Since the uncertainties due to variations are expected to increase in each generation, it will significantly impact the performance of design and consequently the yield. Another challenging issue in the nanometer IC design is the high power consumption due to the greater packing density, higher frequency of operation and excessive leakage power. Moreover, the circuits are usually over-designed to compensate for uncertainties due to variations. The over-designed circuits not only make timing closure difficult but also cause excessive power consumption. For portable electronics, excessive power consumption may reduce battery life; for non-portable systems it may impose great difficulties in cooling and packaging. The objective of my research has been to develop design methodologies to address variations and power dissipation for reliable circuit operation. The proposed work has been divided into three parts: the first part addresses the issues related with power/ground noise induced by clock distribution network and proposes techniques to reduce power/ground noise considering the effects of process variations. The second part proposes an elastic pipeline scheme for random circuits with feedback loops. The proposed scheme provides a low-power solution that has the same variation tolerance as the conventional approaches. The third section deals with discrete buffer and wire sizing for link-based non-tree clock network, which is an energy efficient structure for skew tolerance to variations. For the power/ground noise problem, our approach could reduce the peak current and the delay variations by 50% and 51% respectively. Compared to conventional approach, the elastic timing scheme reduces power dissipation by 20% − 27%. The sizing method achieves clock skew reduction of 45% with a small increase in power dissipation.

Because of the restriction on structure hazard and instruction data dependence, the quantity of NOP instructions fills up a program for VLIW Architectures. This problem causes a waste of program memory, so that an instruction compression mechanism is a must for VLIW Architectures. The vectorized instruction in DVB-T (Digital Video Broadcasting - Terrestrial) DSP will collect the discrete vectors into one continuous vector. This mechanism is based on the software-pipeline of the zero overhead looping mode. It is important to improve the efficiency of instruction fetcher. Additionally, the branch instruction can cause the non-continuous behavior of a program and the damage of the efficiency of instruction fetcher. The mechanism of compressed instructions causes the irregular length of long instruction in fetch packet. The problem becomes difficult designed. The thesis implements a design of improving instruction stream buffer, which can keep the repeat block in buffer. This mechanism overcomes the effects of zero overhead looping and branch instruction. It can also improve the efficiency of continuously fetch instructions. The simulation result shows that the mechanism has a good efficiency in FFT, FIR and DCT.

TCP is the most popular transport layer protocol. When there is congestion in the network, either sender¡¦s TCP or router¡¦s buffer management has its way to resist the penalties of congestion. But each of them achieves this goal in an independent way. In TCP, Tahoe, Reno, New Reno, SACK, Vegas, FACK, and some modifications to TCP to improve performance were proposed. Although they have better performance than previous TCP, the cooperation between different types of TCP is not well. And TCP-unfriendly connections will be adverse to TCP connections. In buffer management, the fairness between different connections can be maintained. But some phenomena will be adverse to TCP connection because of buffer management is TCP-unawareness. In this paper, we show a problem that buffer management scheme may be unfriendly to new connection which is going to join the network with congestion. This problem will incur (1) TCP-unfriendly behavior, (2) alleviating congestion inefficiently, (3) unfairness between two connections. We propose a scheme to alleviate this problem and this scheme is easy to implement with existing buffer management scheme.

In the microprocessor system, the bandwidth problems of instruction stream and data stream are the main causes that limit the performance of the system. Although cache can effectively smooth this problem, the processor still needs more than one clock cycle to get the data. The large hardware cost and power consumption also limit the cache in the embedded system applications. The buffering techniques, such as the loop buffer and the prefetch buffer, can improve the performance in low hardware. Their mechanisms emphasize on the buffering of the continuous data space. For the non-continuous data space accesses caused by the branch instructions, they cannot exploit the reference localities. In this thesis, we propose a new buffering mechanism called as the ABP buffer, which is composed of a buffering mechanism and a prefetching mechanism. The buffering mechanism can effectively buffer the non-continuous data space and replace the buffer lines in a replacement policy, which is suitable for hardware realization. The prefetching mechanism exploits the hit time to prefetch the data that can be used in near future. The simulation and implement results show that the ABP buffer can gain high performance in low hardware and the control parts of the mechanism only occupy 4% of the total hardware.

For any congestion control mechanisms, the most fundamental design objectives are stability and scalability. However, achieving both properties are very challenging in such a heterogeneous environment as the Internet. From the end-users' perspective, heterogeneity is due to the fact that different flows have different routing paths and therefore different communication delays, which can significantly affect stability of the entire system. In this work, we successfully address this problem by first proving a sufficient and necessary condition for a system to be stable under arbitrary delay. Utilizing this result, we design a series of practical congestion control protocols (MKC and JetMax) that achieve stability regardless of delay as well as many additional appealing properties. From the routers' perspective, the system is heterogeneous because the incoming traffic is a mixture of short- and long-lived, TCP and non-TCP flows. This imposes a severe challenge on traditional buffer sizing mechanisms, which are derived using the simplistic model of a single or multiple synchronized long-lived TCP flows. To overcome this problem, we take a control-theoretic approach and design a new intelligent buffer sizing scheme called Adaptive Buffer Sizing (ABS), which based on the current incoming traffic, dynamically sets the optimal buffer size under the target performance constraints. Our extensive simulation results demonstrate that ABS exhibits quick responses to changes of traffic load, scalability to a large number of incoming flows, and robustness to generic Internet traffic.