Since the development of SoC is very fast, how to reduce the power consumption of SoC has become a very important issue. To overcome the issue, the hardware circuit provides multi-voltage method to reduce task power consumption. On the other hand, the software tool decides the task voltage to minimize the total power consumption. In this thesis, we developed a genetic algorithm to solve the voltage mapping problem of multi-voltage systems. This goal of this genetic algorithm is to consider the time constraints or power constraints in the multi-voltage system to find the better solution. In order to apply genetic algorithm to solve voltage mapping problem, we build a compilation flow that embeds in the genetic algorithm. To demonstrate the efficiency of proposed approach, we apply compilation flow to two examples. One is multi-voltage reconfigurable processor system. The processor in the system provides multi-mode and multi-voltage. The multi-mode can reduce the execution time of tasks with high parallelism. Multi-voltage can reduce the power consumption of task by decreasing voltage. We use genetic algorithm to choose task mode to achieve the performance goal. Another is multiple multi-voltage processors. We use list-scheduling to find the task schedule and use genetic algorithm to choose the task voltage. This method can reduce total power consumption. According to the experimental results, the proposed genetic algorithm can reduce the power consumption efficiently.

The ability to design is the distinguishing characteristic of an engineer. Recent research has increased our understanding of both the engineering design process and effective means for teaching that process to neophyte design engineers. In that spirit, a design methodology was developed at the Institute for Innovation and Design in Engineering (IIDE), Texas A&M University. At the core of this approach is a design philosophy based on the cognitive skills of Abstraction, Critical Parameter Identification, and Questioning. This philosophy along with the design process is taught in the senior undergraduate design and graduate design courses. The goal of the methodology is not only to teach the design process to novice designers but also to instill in them the design philosophy that would enable them to perform design effectively and innovatively in any area of specialty. In this dissertation the design philosophy along with its role in the design methodology is explained. The Need Analysis and the Conceptual Design stages of the IIDE methodology are elaborated. The weaknesses in these stages are identified and addressed, by developing and incorporating design methods and techniques that fit the spirit and framework of the IIDE design methodology. The Object Function Method was developed to address certain aspects at the Need Analysis stage. There was need for an effective concept searching method within the Concept Design stage of the IIDE design methodology. This is addressed by the development of new search techniques and methods for effective concept discovery during concept searching. The usage and application of these methods and techniques is explained in detail along with examples. Additionally, this dissertation contains the results of a study conducted with two groups of senior design students, those who have been through the process and those who have not, to evaluate the effectiveness of applying the IIDE design philosophy and performing the Need Analysis and Conceptual Design stages for the given design challenge. The goal of the study was to investigate the relationship, if any, between the degree to which these aspects of the design methodology were followed and the quality of the resulting design solutions produced.

A power system protection system consists, at least, of an instrument trans- former, a protective device (relay), and a circuit breaker. Conventional instrument transformers bring currents and voltages from power network levels to much lower scaled-down replicas that serve as input signals to protective relays. The relay's function is to measure input signals (or a relationship among them in some cases) and compare them to defined operating characteristic thresholds (relay settings) to quickly decide whether to operate associated circuit breaker(s). Existing protection systems within a substation are based on a hardwired interface between instrument transformers and protective relays. Recent development of electronic instrument transformers and the spread of digital relays allow the development of an all-digital protection system, in which the traditional analog interface has been replaced with a digital signal connected to digital relays through a digital communication link (process bus). Due to their design, conventional instrument transformers introduce distortions to the current and voltage signal replicas. These distortions may cause protective relays to misoperate. On the other hand, non-conventional instrument transformers promise distortion-free replicas, which, in turn, should translate into better relay performance. Replacing hardwired signals with a communication bus also reduces the significant cost associated with copper wiring. An all-digital system should provide compatibility and interoperability so that different electronic instrument transformers can be connected to different digital relays (under a multi-vendor connection) Since the novel all-digital system has never been implemented and/or tested in practice so far, its superior performance needs to be evaluated. This thesis proposes a methodology for performance and compatibility evaluation of an all-digital protection system through application testing. The approach defines the performance indices and compatibility indices as well as the evaluation methodology.

In recent years, a theme for generally discussion in IC design domain is how to do the efficient verification in complex SoC environment and raise the confidence when chip taped-out. But when we face the different abstraction levels of verification environment like the System Modeling Level, Register Transfer Level, FPGA Emulation Level and Chip Level verification environment, how to unifiy test-patterns and makes them can be reused and do mutual-verification in different abstraction level verification environments is our main topic. Therefore, this thesis proposed a verification methodology that based on the 3D graphics SoC and unified the test patterns that let the different abstraction levels of verification environment can use the same test patterns. And to face the exetensive test patterns of 3DG SoC, we also proposed an automatic verification mechanism which can run the simulation and compare the simulation results automatically and improve the verification efficiency. Finally, we also share the 3DG SoC integration and verification experience from front-end to back-end, hope to makes everyone understand the related flow from RTL design to test-chip testing.

No description available.

Thesis (J.C.D.)--Pontificia Università Lateranense. / At head of title: Institutum utriusque iuris, Theses ad doctoratum in iure canonico. Includes bibliographical references (p. [441]-466).

While political scientists have traditionally examined social influence through social network or contextual studies, this dissertation argues for the use of spatial econometrics as an alternative approach. While spatial econometrics is not new to political science, the dissertation attempts to broaden its application by exploring spaces based on geography, demographic characteristics, and ideology. Social influence can be understood as a form of spatial interdependence among individuals in these spaces and can be analyzed as spatial autocorrelation. In the dissertation, I discuss the dimensions of the three spaces, what might account for mutual influence in these spaces, how to measure distances in these spaces, and how to use these distances for estimating social influence in models of political attitudes using ANES data. By taking a broader approach to space, I show that spatial econometrics can offer many advantages over more conventional approaches. / text

published_or_final_version / Politics and Public Administration / Master / Master of Public Administration

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