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Pico-Cellular architecture fully reuses frequency to increase network capacity. However, it will increase the occurance of Handoff due to the small range of cell. Previous works in channel allocations can reduce blocking probability of handoff call, but it may increase blocking probability of new call. As a result, channel utilization is decreased because they can not adapt to network changes. In this thesis, we present a Dynamic Channel Allocation Mechanism with priority support. All channels and calls are divided into high and low priority. If there is no high_priority channel for high_priority call, high_priority call may downgrade its priority by sacrificing some QoS to utilize low_priority channels. We define two new array for network information status, one is next_cell state, and the other is the transition probability. Next_cell state is used to save prior M Cell_Ids where handoff calls may move to. Transition probability is used to save the probabilities for active calls moving to other neighboring cells. According to next_cell state and transition probability, we can accurately predict the probabilities for mobile hosts moving to other neighboring cells. Therefore, we can dynamically adjust bandwidth reservation requests sending to neighboring cells by the latest transition probability and the number of active calls in this cell. We analyze the proposed mechanism through a mathematical model. In the model, we build a four-dimension Markov Chain and use MATLAB[41] tool to evaluate blocking probability, channel throughput and utilization. We found out that blocking probability of handoff call can be decreased and channel utilization can be increased through the proposed channel allocation mechanisms with high and low priority support.

It is known that to pursuit end-to-end QoS of a class-based traffic flow is inefficient in Differentiated Service Networks. Therefore in this thesis, we propose an effective throughput-recovery mechanism to allow high-priority traffic flow to receive suitable resource allocation, and hence the end-to-end QoS is guaranteed. The proposed throughput-recovery mechanism assures a predefined minimum departure rate of low-latency EF dataflow. It consists of two parts. The first part is referred to as the feedback self-adaptive mechanism, where the egress node measures and monitors throughput of EF dataflow to decide whether to send the control messages to ingress node. When ingress node receives the control messages, it will reallocate the resources to improve EF throughput. The second part is referred to as the dynamic weight adjustment mechanism, which can prevent EF packets from dropping when congestion occurs in the core routers. For the purpose of demonstration, we build a mathematical model and use NS-2 simulator. We have proved our throughput-recovery mechanism is effective in improving the throughput of EF traffic flow. Finally, we modify the traditional WRR such that it can adjust weight based on the delay requirements.

Abstract One of the features in Taiwan market is price competition. What makes it even worse are the outflow of investment, more demand on environmental protection, increase of labor cost, and the limit of national policy. These factors make business hardly earn profits. And therefore, how to gain reasonably with limited resources and survive in the competition are the difficulties we need to overcome in Taiwan. Printed Circuit Board played a key role in ¡§Taiwan Financial Miracle¡¨ for the past 10 years. However, the manufacturers now have no choice but to search for new niche to meet the change on the whole business environment. The headquarters staying in Taiwan have to face even more harsh conditions, which come from the demand of cost-down, the price competitions among the same industry. Therefore, it becomes essential to adjust Product Mixed in order to fit the insufficient Product Resources. My study puts focus on ¡§Most Constrained Station¡¨ from the Theory of Constraint. It helps PCB manufacturers, who suffers slim profit, find out the best Products Mixed in accordance of Throughput Contribution. Each product brings different profit and cost. Some may share common resources, and some may not, when they are put in the process line. Therefore, to continue forward in the age of slim-profit, the complex of Product Mixed and earnings becomes prominent. Studying Theory of Constraint, I aim to bring forth the best solution on processing contribution by means of figuring out the Throughput Chain in Most Constrained Station and analysis of application on Most Constrained Station. And then I will conclude with the best production strategy for the PCB manufacturer as the main thesis of the research.

Vertex shader, one of the core parts in 3D graphics systems, is to speed up the operations of coordinate transformation and lighting in 3D graphics pipeline, and vector ALU is the key part of a vertex shader. This thesis proposes several unified architectures that integrate the floating-point vector arithmetic unit and special function unit in order to share some hardware resource. We propose three different architectures for the design of the unified vector ALU. The first architecture includes a single-instruction-multiple-data (SIMD) vector arithmetic unit, and uses table-based method with first-order approximation to calculate some special functions. The second architecture use higher-order approximation to reduce the table sizes and share the floating-point multipliers in the SIMD vector unit. The proposed third architecture has two copies of hardware that can compute two dot-product operations in parallel and thus increase the throughput of the matrix computation by a factor of two. Furthermore, the two dot-product units can be used to perform the interpolation for special function calculation.

In a WiMAX network, four traffic types with different priorities are defined. They are Unsolicited Grant Service (UGS), real-time Polling Service (rtPS), non-real-time Polling Service (nrtPS), and Best Effort (BE). In this thesis, we propose a Dynamic Bandwidth Allocation (DBA) scheme for BS to schedule the four above-mentioned traffic types. By adopting Deficit Round Robin (DRR) scheduling, DBA first assigns minimum quantum to each traffic type for transmission. When rtPS packets exceed their delay constraints, without sacrificing the minimum requirements of nrtPS and BE traffic, DBA borrows some quantum from nrtPS and BE to satisfy the delay requirements of rtPS traffic. When nrtPS packets can not reach the minimum transmission rate, without starving the BE traffic, DBA borrows some quantum from BE to support the required throughput of nrtPS traffic. According to the history record of borrowed quantum, DBA dynamically adjusts the assigned quantum for the three traffic types. For the purpose of evaluation, we use NS-2 to simulate the proposed DBA. We adjust the traffic load to analyze the performance in terms of average packet delay, average throughput, and average packet loss ratio. The simulation results show that the DBA, in comparison to a previous work, can promise the delay constraints of rtPS, maintain the average throughput of nrtPS, and avoid the starvation of BE, when the traffic load is high.

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An advancement of the two stage growth recipe for the fabrication of CIGS solar cells was developed. The developed advancement was inconsistent in producing samples of similar stoichiometry. This was a huge barrier for up scaling the process as the behavior of devices would be different due to variation in stoichiometry. Samples with reproducible stoichiometry were obtained once the heating rate of elements, selenium in particular was better understood. This is mainly attributed to the exponential increase of selenium flux after its evaporation temperature. Monitoring the selenium flux was vital in getting constant selenium fluxes. Few changes to the growth recipe were induced to optimize the amount of selenium being used. Depositions were done using constant selenium to metal flux ratio of 5. Elemental tradeoffs were observed as a result of the growth recipe change. These tradeoffs are in favor of the two stage growth recipe. The solar cells were fabricated on a soda lime glass substrate with a molybdenum back contact. Improper sample cleaning and storage were found to affect the deposition outcome of the molybdenum back contact. This also had a cascading effect on the absorber layer. Residual precipitates during deposition of CdS were avoided by increasing the spinner speed which increased the reaction rate. This is attributed to the growth of CdS either by cluster-by-cluster growth or by ion-by-ion growth. SEM, EDS were some important tools used to characterize the devices. EDS in particular, was used extensively at different stages throughout the growth process to ensure that we were heading in the right direction. Current-voltage (I-V) measurements were done to study the solar cell performance under light and dark.

Modern computer systems are power or energy limited. While the number of transistors per chip continues to increase, classic Dennard voltage scaling has come to an end. Therefore, architects must improve a design's energy efficiency to continue to increase performance at historical rates, while staying within a system's power limit. Throughput processors, which use a large number of threads to tolerate memory latency, have emerged as an energy-efficient platform for achieving high performance on diverse workloads and are found in systems ranging from cell phones to supercomputers. This work focuses on graphics processing units (GPUs), which contain thousands of threads per chip. In this dissertation, I redesign the on-chip storage system of a modern GPU to improve energy efficiency. Modern GPUs contain very large register files that consume between 15%-20% of the processor's dynamic energy. Most values written into the register file are only read a single time, often within a few instructions of being produced. To optimize for these patterns, we explore various designs for register file hierarchies. We study both a hardware-managed register file cache and a software-managed operand register file. We evaluate the energy tradeoffs in varying the number of levels and the capacity of each level in the hierarchy. Our most efficient design reduces register file energy by 54%. Beyond the register file, GPUs also contain on-chip scratchpad memories and caches. Traditional systems have a fixed partitioning between these three structures. Applications have diverse requirements and often a single resource is most critical to performance. We propose to unify the register file, primary data cache, and scratchpad memory into a single structure that is dynamically partitioned on a per-kernel basis to match the application's needs. The techniques proposed in this dissertation improve the utilization of on-chip memory, a scarce resource for systems with a large number of hardware threads. Making more efficient use of on-chip memory both improves performance and reduces energy. Future efficient systems will be achieved by the combination of several such techniques which improve energy efficiency. / text

Recombinant antibodies and antibody fragments have become powerful tools for therapy, in vivo and in vitro diagnostics, and laboratory research. However, the production of antibody fragments in high yield for preclinical and clinical trials can be a serious bottleneck in drug discovery. This dissertation describes the development of novel screening systems for isolating antibody fragments and alternatively, E. coli genes, that facilitate expression in E. coli. In the first part of this work, we have developed a screening system for isolating Fab mutants exhibiting 4~5 fold higher expression level at 37oC compared to the parental Fab, by utilizing the APEx 2-hybrid system and multi-color FACS as a screening tool. In the APEx 2-hybrid system, the bacterial periplasm constitutes the milieu for the association of membrane-anchored bait protein and solubly expressed, epitope-tagged prey protein. Upon disruption of the outer membrane, only prey proteins that bind to the bait remain cell-associated and are detected by flow cytometry using fluorescently labeled anti-epitope antibodies. In the second part of this work we developed a new strategy to engineer scFv that can be expressed in soluble and active form in the absence of disulfide bonds. This was achieved using a strain incapable of forming disulfide bonds in proteins expressed in its periplasm in combination with the APEx 2-hybrid system. The selected clones exhibited higher solubility, activity, and stability than that of the wild type scFv in the reducing condition of the cytoplasm. Finally, we sought to isolate E. coli gene fragments that can enhance IgG production in the periplasm of E. coli by a newly developed screening system based on soluble expression of IgG and E. coli genomic fragments. The isolated gene fragments, which are located between moeA and iaaA in the E. coli chromosome, improved the total expression of polypeptides of IgG and also assembly of IgG. / text