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Single electron transistors (SET) have attracted significant attention as a potential building block for post CMOS nanoelectronic devices. However, lack of reproducible and parallel fabrication approach and room temperature operation are the two major bottlenecks for practical realization of SET based devices. In this thesis, I demonstrate large scale single electron transistors fabrication techniques using solution processed single wall carbon nanotubes (SWNTs) and studied their electron transport properties. The approach is based on the assembly of individual SWNTs via dielectrophoresis (DEP) at the selected position of the circuit and formation of tunnel barriers on SWNT. Two different techniques: i) metal-SWNT Schottky contact, and ii) mechanical templating of SWNTs were used for tunnel barrier creation. Low temperature (4.2K) transport measurement of 100 nm long metal-SWNT Schottky contact devices show that 93% of the devices with contact resistance (RT) > 100 K? show SET behavior. Majority (90%) of the devices with 100 K? < RT < 1 M?, show periodic, well-de?ned Coulomb diamonds with a charging energy ~ 15 meV, represents single electron tunnelling through a single quantum dot (QD), defined by the top contact. For high RT (> 1M?), devices show multiple QDs behaviors, while QD was not formed for low RT ( < 100 K?) devices. From the transport study of 50 SWNT devices, a total of 38 devices show SET behavior giving an yield of 76%. I also demonstrate room temperature operating SET by using mechanical template technique. In mechanical template method individual SWNT is placed on top of a Al/Al2O3 local gate which bends the SWNT at the edge and tunnel barriers are created. SET devices fabricated with a template width of ~20 nm shows room temperature operation with a charging energy of ~150 meV. I also discussed the detailed transport spectroscopy of the devices.

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XLI

The semiconductor industry scaling has mainly been driven by Moore's law, which states that the number of transistors on a single chip should double every year and a half to two years. Beyond 2011, when the channel length of the Metal Oxide Field effect transistor (MOSFET) approaches 16 nm, the scaling of the planar MOSFET is predicted to reach its limit. Consequently, a departure from the current planar MOSFET on bulk silicon substrate is required to push the scaling limit further while maintaining electrostatic control of the gate over the channel. Alternative device structures that allow better control of the gate over the channel such as reducing short channel effects, and minimizing second order effects are currently being investigated. Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to parasitic effects from the bulk. The doping of the source and drain regions and the redistribution of the dopants in the channel greatly impact the electrical characteristics of the fabricated device. Thus, in nano-scale and reduced dimension transistors, a tight control of doping levels and formation of pn junctions is required. Therefore, deeper understanding of the lateral component of the diffusion mechanisms and interface effects in these lower dimensional structures compared to the bulk is necessary. This work focuses on studying the dopant diffusion mechanisms in Silicon nanomembranes (2D), nanoribbons (â 1.Xâ D), and nanowires (1D). This study also attempts to benchmark the 1D and 2D diffusion against the well-known bulk (3D) diffusion mechanisms. / Master of Science

[pt] Este trabalho trata dos efeitos das não-linearidades de transistores de efeito de campo utilizados em amplificadores de microondas. Para tanto, o transistor é modelado por um circuito não- linear equivalente, cujos elementos são determinados através da medição dos parâmetros espalhamento do mesmo, na faixa de 3 GHz a 9 GHz, e com o auxílio de um programa de otimização de circuitos e outro de ajuste de curvas. O método de análise utilizado é o da expansão em série de Volterra, para o qual foi desenvolvido um programa computacional que permite a determinação dos ganhos de transdução e das potências de saída na freqüência fundamental e no terceiro produto de intermodulação, bem como do ponto de 1dB de compressão de ganho, da taxa de distorção de intermodulação de terceira ordem. Esse programa permite, ainda, a verificação da influência das impedâncias de fechamento fora da faixa, nas características de distorção de intermodulação. Através dessa análise pôde-se verificar que as terminações fora da faixa exercem pouca ou nenhuma influência nas características de distorção de intermodulação, com exceção das terminações na freqüência diferença, (freqüência de diferença = freqüência 2 - freqüência 1), onde pôde-se constatar uma redução de até 8dB no nível do terceiro produto de intermodulação, para uma escolha apropriada das impedâncias de fechamento nessa freqüência. Esses resultados, contudo, não podem ser considerados definitivos, uma vez que o modelo adotado não levou em consideração o fato do FET utilizado ser pré-adaptado. Também, devido ao transistor ter-se danificado durante as medições de intermodulação, tais resultados não puderam ser comprovados experimentalmente. / [en] This work deals with the effects of non-linear ities of field-effect transistors used in microwave amplifiers. To do so, the transistor is modeled by a non-linear equivalent circuit, with its components determined through the measurement of its scattering parameters, in the range of 3 GHz to 9GHz, and with the aid of a circuit optimization program and another for curve fitting. The method of analysis used is the Volterra series expansion, for which a computer program was developed, permitting the determination of the transducer gains and output powers in the fundamental frequency, and in the third-order intermodulation product, as well as the 1 dB compression point, the third-order intermodulation distortion ratio, and the third-order intercept point. This program also allows for the verification of the influence of out-of-band terminating impedances on the intermodulation distortion characteristics. Through this analysis it was possible to verify that the out-of-band terminations have little or no influence on the intermodulation distortion characteristics, with the exception of the terminations in the difference frequency, (difference frequency = frequency 2 - frequency 1), for which it was found a decrease of up to 8 dB in the third- order intermodulation product level, for the appropriate choice of these impedances. These results, however, cannot be said to represent the real behavior of the FET since the model used did not account for the internal matching of the device. Also, due to the fact that the transistor was damaged during the intermodulation measurements, such results could not be verified experimentally.

Understanding structure-property relationship of molecules is imperative for designing efficient materials for organic semiconductors. Organic semiconductors are based on π-conjugated molecules, either small molecules or macromolecules such as dendrimers or polymers. Charge transport through organic materials is one of the most important processes that drive organic electronic devices. We have investigated the charge transport properties in various molecular designs based on dendrons, dendron-rod-coil molecular triads, and conjugated oligomers. The charge transport properties were studied using bottom contact field effect transistors, in which the material was deposited by spin coating. In case of dendrons, their generation and density of charge transporting functionalities were found to play a significant role in influencing the charge transport properties. In case of macromolecules such as dendron-rod-coil molecules, the solid state morphology plays a significant role in influencing the charge transport properties. While these molecules exhibit only electron transporting behavior in field-effect transistor measurements, ambipolar charge transport is observed in the diode configuration. Short conjugated oligomers, based on donor-acceptor-donor design, provide model systems for conjugated polymers. Effect of varying the donor functionality on optoelectronic and charge transport properties was studied in short donor-acceptor-donor molecules. While donor-acceptor-donor molecules are well known in the literature, the effect of molecular composition on the charge transport properties is not well understood. We designed molecules with 2,1,3-benzothiadiazole as the acceptor and thiophene based donor functionalities. These molecules exhibit a reduced bandgap, good solution processability and charge mobility making them interesting systems for application in organic photovoltaics. Cyclopentadithiophene (CPD) based materials have been widely utilized as organic semiconductors due to their planar nature which favors intermolecular charge transport. While most CPD based materials are hole transporting, incorporation of electron withdrawing fluorinated substituents imparts n-type behavior to these molecules. This change in charge transport properties has often been attributed to the lowering of the LUMO energy level due to the increased electron affinity in the molecule. We designed CPD based semiconductors in which the bridgehead position was functionalized with electron withdrawing ketone or dicyanomethylene group and the -positions were substituted with phenyl or pentafluorophenyl groups. Both the phenyl substituted molecules are p-type materials, even though the dicyanomethylene group lowers the LUMO by 500 meV as compared to the carbonyl compound. The pentafluorophenyl substituted molecules are n-type materials even as their LUMO energy levels are about 300 meV higher than the corresponding phenyl substituted molecules. This indicates that charge transport behavior is not an exclusive function of the frontier orbital energy levels.

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The continued scaling of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has led to a rapid increase in compute power. Resulting from increases in device densities and advances in materials and transistor design, integrated circuit (IC) performance has continued to improve while operational power (VDD) has been substantially reduced. However, as feature sizes approach the atomic length scale, fundamental limitations in switching characteristics (such as subthreshold slope, SS, and OFF-state power dissipation) pose key technical challenges moving forward. Novel material innovations and device architectures, such as group IV and III-V materials and tunnel field-effect transistors (TFETs), have been proposed as solutions for the beyond Si era. TFETs benefit from steep switching characteristics due to the band-to-band tunneling injection of carriers from source to channel. Moreover, the narrow bandgaps of III-V and germanium (Ge) make them attractive material choices for TFETs in order to improve ON-state current and reduce SS. Further, Ge grown on InₓGa₁₋ₓAs experiences epitaxy-induced strain (ε), further reducing the Ge bandgap and improving carrier mobility. Due to these reasons, the ε-Ge/InₓGa₁₋ₓAs system is a promising candidate for future TFET architectures. In addition, the ability to tune the bandgap of Ge via strain engineering makes ε-Ge/InₓGa₁₋ₓAs heterostructures attractive for nanoscale group IV-based photonics, thereby benefitting the monolithic integration of electronics and photonics on Si. This research systematically investigates the material, optical, and heterointerface properties of ε-Ge/InₓGa₁₋ₓAs heterostructures on GaAs and Si substrates. The effect of strain on the heterointerface band alignment is comprehensively studied, demonstrating the ability to modulate the effective tunneling barrier height (Ebeff) and thus the threshold voltage (VT), ON-state current, and SS in future ε-Ge/InₓGa₁₋ₓAs TFETs. Further, band structure engineering via strain modulation is shown to be an effective technique for tuning the emission properties of Ge. Moreover, the ability to heterogeneously integrate these structures on Si is demonstrated for the first time, indicating their viability for the development of next-generation high performance, low-power logic and photonic integrated circuits on Si. / Master of Science