[pt] Mesmo com a evolução dos dispositivos de armazenamento e comunicação, mantém-se crescente a demanda por mecanismos de compressão de dados mais eficientes. Entre os compressores baseados na freqüência de símbolos, destacam - se os códigos livres de prefixo, que são executados por vários métodos compostos de diferentes algoritmos e também apresentam bom desempenho em uso isolado. Muitas pesquisas trouxeram maior eficiência aos códigos de prefixo, centradas, sobretudo, na redução do espaço de memória necessário e tempo gasto durante a descompressão. O presente trabalho abrange códigos de prefixos e respectivas técnicas de descompressão visando propor um novo codificador, o compressor LTL, que utiliza códigos com restrição de comprimento para reduzir o espaço de memória da tabela Look-up, eficiente método de decodificação. Devido ao uso de códigos restritos, é admitido um pequeno decréscimo nas taxas de compressão para possibilitar uma decodificação mais rápida. Os resultados obtidos indicam perda de compressão inferior a 11 por cento para um modelo baseado em caracteres, com velocidade média de decodificação cinco vezes maior que a de um decodificador canônico. Embora, para um modelo de palavras, o ganho médio de velocidade seja de 3,5, constata-se que, quando o número de símbolos é muito grande, o tamanho da tabela look-up impossibilita uma utilização eficiente da memória cache. Assim, o LTL é indicado para substituir quaisquer códigos de prefixo baseados em caracteres cuja aplicação requer agilidade no processo de descompressão. / [en] Even with the evolution of communication and storage devices, the use of complex data structures, like video and hypermedia documents, keeps increasing the demand for efficient data compression mechanisms. Prefix codes are one of the most known compressors, since they are executed by some compression methods that group different algorithms, besides presenting a good performance when used separately. A lot of approaches have been tried to improve the decoding speed of these codes. One major reason is that files are compressed and updated just a few times, whereas they have to be decompressed each time they are accessed. This work presents prefix codes and their decoding techniques in order to introduce a new coding scheme. In this scheme length-restricted codes are used to control the space requirements of the Look-up table, an efficient and fast prefix codes decoding method. Since restricted codewords are used, a small loss of compression efficiency is admitted. Empirical experiments indicate that this loss in the coded text is smaller than 11 percent if a character based model is used, and the observed average decoding speed is five times faster than the one for canonical codes. For a word based model, the average decoding speed is 3,5 times faster than a canonical decoder, but it decreases when a large number of symbols is used. Hence, this method is very suitable for applications where a character based model is used and extremely fast decoding is mandatory.

Aquesta Tesi Doctoral se centra en el disseny d'un nou linealitzador de Predistorsió Digital (Digital Predistortion - DPD) capaç de compensar la dinàmica i els efectes no lineals introduïts pels Amplificadors de Potència (Power Amplifiers - PAs). Un dels trets més rellevants d'aquest nou predistorsionador digital i adaptatiu consisteix en ser deduïble a partir d'un model de PA anomenat Nonlinear Auto-Regressive Moving Average (NARMA). A més, la seva arquitectura multi-LUT (multi-Taula) permet la implementació en un dispositiu Field Programmable Gate Array (FPGA).La funció de predistorsió es realitza en banda base, per tant, és independent de la banda freqüencial on es durà a terme l'amplificació del senyal de RF, el que pot resultar útil si tenim en compte escenaris multibanda o reconfigurables. D'altra banda, el fet que aquest DPD tingui en compte els efectes de memòria introduïts pel PA, representa una clara millora de les prestacions aconseguides per un simple DPD sense memòria. En comparació amb d'altres DPDs basats en models més computacionalment complexos, com és el cas de les xarxes neuronals amb memòria (Time-Delayed Neural Networks - TDNN), la estructura recursiva del DPD proposat permet reduir el nombre de LUTs necessàries per compensar els efectes de memòria del PA. A més, la seva estructura multi-LUT permet l'escalabilitat, és a dir, activar or desactivar les LUTs que formen el DPD en funció de la dinàmica que presenti el PA.En una primera aproximació al disseny del DPD, és necessari identificar el model NARMA del PA. Un dels majors avantatges que presenta el model NARMA és la seva capacitat per trobar un compromís entre la fidelitat en l'estimació del PA i la complexitat computacional introduïda. Per reforçar aquest compromís, l' ús d'algoritmes heurístics de cerca, com són el Simulated Annealing o els Genetic Algorithms, s'utilitzen per trobar els retards que millor caracteritzen la memòria del PA i per tant, permeten la reducció del nombre de coeficients necessaris per caracteritzar-la. Tot i així, la naturalesa recursiva del model NARMA comporta que, de cara a garantir l'estabilitat final del DPD, cal dur a terme un estudi previ sobre l'estabilitat del model.Una vegada s'ha obtingut el model NARMA del PA i s'ha verificat l'estabilitat d'aquest, es procedeix a l'obtenció de la funció de predistorsió a través del mètode d'identificació predictiu. Aquest mètode es basa en la continua identificació del model NARMA del PA i posteriorment, a partir del model obtingut, es força al PA perquè es comporti de manera lineal. Per poder implementar la funció de predistorsió en la FPGA, cal primer expressar-la en forma de combinacions en paral·lel i cascada de les anomenades Cel·les Bàsiques de Predistorsió (BPCs), que són les unitats fonamentals que composen el DPD. Una BPC està formada per un multiplicador complex, un port RAM dual que actua com a LUT (taula de registres) i un calculador d'adreces. Les LUTs s'omplen tenint en compte una distribució uniforme dels continguts i l'indexat d'aquestes es duu a terme mitjançant el mòdul de l'envoltant del senyal. Finalment, l'adaptació del DPD consisteix en monitoritzar els senyals d'entrada i sortida del PA i anar duent a terme actualitzacions periòdiques del contingut de les LUTs que formen les BPCs. El procés d'adaptació del contingut de les LUTs es pot dur a terme en la mateixa FPGA encarregada de fer la funció de predistorsió, o de manera alternativa, pot ser duta a terme per un dispositiu extern (com per exemple un DSP - Digital Signal Processor) en una escala de temps més relaxada. Per validar l'exposició teòrica i provar el bon funcionalment del DPD proposat en aquesta Tesi, es proporcionen resultats tant de simulació com experimentals que reflecteixen els objectius assolits en la linealització del PA. A més, certes qüestions derivades de la implementació pràctica, tals com el consum de potència o la eficiència del PA, són també tractades amb detall. / This Ph.D. thesis addresses the design of a new Digital Predistortion (DPD) linearizer capable to compensate the unwanted nonlinear and dynamic behavior of power amplifiers (PAs). The distinctive characteristic of this new adaptive DPD is its deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA behavioral model and its particular multi look-up table (LUT) architecture that allows its implementation in a Field Programmable Gate Array (FPGA) device.The DPD linearizer presented in this thesis operates at baseband, thus becoming independent on the final RF frequency band and making it suitable for multiband or reconfigurable scenarios. Moreover, the proposed DPD takes into account PA memory effects compensation which representsan step forward in overcoming classical limitations of memoryless predistorters. Compared to more computational complex DPDs with dynamic compensation, such Time-Delayed Neural Networks (TDNN), this new DPD takes advantage of the recursive nature of the NARMA structure to relax the number of LUTs required to compensate memory effects in PAs. Furthermore, its parallel multi-LUT architecture is scalable, that is, permits enabling or disabling the contribution of specific LUTs depending on the dynamics presented by a particular PA.In a first approach, it is necessary to identify a NARMA PA behavioral model. The extraction of PA behavioral models for DPD linearization purposes is carried out by means of input and output complex envelope signal observations. One of the major advantages of the NARMA structure regards its capacity to deal with the existing trade-off between computational complexity and accuracy in PA behavioral modeling. To reinforce this compromise, heuristic search algorithms such the Simulated Annealing or Genetic Algorithms are utilized to find the best sparse delays that permit accurately reproducing the PA nonlinear dynamic behavior. However, due to the recursive nature of the NARMA model, an stability test becomes a previous requisite before advancing towards DPD linearization.Once the PA model is identified and its stability verified, the DPD function is extracted applying a predictive predistortion method. This identification method relies just on the PA NARMA model and consists in adaptively forcing the PA to behave as a linear device. Focusing in the DPD implementation, it is possible to map the predistortion function in a FPGA, but to fulfill this objective it is first necessary to express the predistortion function as a combined set of LUTs.In order to store the DPD function into a FPGA, it has to be stated in terms of parallel and cascade Basic Predistortion Cells (BPCs), which are the fundamental building blocks of the NARMA based DPD. A BPC is formed by a complex multiplier, a dual port RAM memory block acting as LUT and an address calculator. The LUT contents are filled following an uniform spacing procedure and its indexing is performed with the amplitude (modulus) of the signal's envelope.Finally, the DPD adaptation consists in monitoring the input-output data and performing frequent updates of the LUT contents that conform the BPCs. This adaptation process can be carried out in the same FPGA in charge of performing the DPD function, or alternatively can be performed by an external device (i.e. a DSP device) in a different time-scale than real-time operation.To support all the theoretical design and to prove the linearization performance achieved by this new DPD, simulation and experimental results are provided. Moreover, some issues derived from practical experimentation, such as power consumption and efficiency, are also reported and discussed within this thesis.

No description available.

This thesis describes the development and validation of a look-up table capable of predicting heat transfer to water flowing vertically upward in a circular tube in the trans-critical pressure range from 19 to 30 MPa. The table was based on an extensive and screened experimental database and its trends were smoothened to remove unrealistic scatter and physically implausible discontinuities. When compared to other prediction methods, the present look-up table approximated the experimental data closer in values and trends. Moreover, unlike existing prediction methods, the table applies not only to normal heat transfer conditions but also to conditions with heat transfer deterioration and enhancement. A separate multi-fluid look-up table for trans-critical heat transfer was also developed, which besides the existing water database incorporated new measurements in carbon dioxide; the latter were collected at the University of Ottawa supercritical flow loop under conditions of interest for the current Super-Critical Water-Cooled Reactor designs, for which few water data were available in the literature. Existing fluid-to-fluid scaling laws were tested and two additional sets of scaling laws were proposed, which are applicable not only to the supercritical pressure region, but also to the high pressure subcritical region. The multi-fluid table is applicable to water at conditions of normal and abnormal heat transfer, but its applicability to model fluids is restricted to the normal heat transfer mode.

<p>This thesis is funded by the IBM Center for Advanced Studies</p> / <p>A large number of scientific applications rely on the computing of logarithm. Thus, accelerating the speed of computing logarithms is significant and necessary. To this end, we present the realization of a pipelined Logarithm Computation Unit (LCU) in hardware that uses lookup table and interpolation techniques. The presented LCU supports single precision arithmetic with fixed accuracy and speed. We estimate that it can generate 2.9G single precision values per second under a 65nm fabrication process. In addition, the accuracy is at least 21 bits while lookup table size is about 7.776KB. To the best of our knowledge, our LCU achieves the fastest speed at its current accuracy and table size.</p> / Master of Science (MSc)

Ferroelectric field-effect transistors (FeFET) based on hafnium oxide offer great opportunities for Logic-in-Memory applications, due to their natural ability to combine logic (transistor) and memory (ferroelectric material), their low-power operation, and CMOS compatible integration. Besides aggressive scaling, dense integration of FeFETs is necessary to make electronic circuits more area-efficient. This paper investigates the impact of ultra-dense co-integration of a FeFET and an n-type selector FET, sharing the same active area, arranged in a 2TNOR memory array. The examined FeFETs exhibit a very similar switching behavior as FeFETs arranged in a standard AND-type array, indicating that the ultra-dense co-integration does not degrade the FeFET performance, and thus, paves the path to a very fine-grained, ultra-dense Logic-in-Memory implementation. Based on this densely integrated 2TNOR array we propose a very compact design of a 4-to-1 multiplexer with a build-in look-up table, thus directly merging logic and memory.

Abstract The aims with this report are to document the upgrade and development of new software for the distance laboratory at Blekinge Tekniska Högskola. The work has been focused on implementing the identification number in a microcontroller, to read its data from a so called look-up table and to be able to control digital components through a serial bus (SPI). The look-up table is a list of data from which the software reads data for the different types of printed circuit boards in the hardware component of the distance laboratory is in focus. The results of the report are an implemented, upgraded version of the software and all three aims has been accomplished. Sammanfattning Syftet med detta arbete har varit att utveckla och uppgradera en ny mjukvara till distanslaboaratoriet på Blekinge Tekniska Högskola, genom att implementera adressen till en microcontroller, att läsa dess data från en så kallad look-up table, samt att kunna styra digitala komponenter med en seriell buss (SPI). Fokus i programmeringen har legat på look-up table, vilket är en datalista som mjukvaran läser funktionsdata från för de olika korttyperna i matrisen. Resultatet är en implementerad, uppgraderad version av mjukvaran och alla tre målen har gått att genomföra.

Non-isothermal compositional two-phase flow is considered to be one of the fundamental physical processes in the field of water resources research. The strong non-linearity and discontinuity emerging from phase transition phenomena pose a serious challenge for numerical modeling. Recently, Lauser et al.[1] has proposed a numerical scheme, namely the Nonlinear Complementary Problem (NCP), to handle this strong non-linearity. In this work, the NCP is implemented at both local and global levels of a Finite element algorithm. In the former case, the NCP is integrated into the local thermodynamic equilibrium calculation. While in the latter one, it is formulated as one of the governing equations. The two different formulations have been investigated through several well established benchmarks and analyzed for their efficiency and robustness. In the second part of the thesis, the presented numerical formulations are applied for application and process studies in the context of nuclear waste disposal in Switzerland. Application studies comprehend the coupling between multiphase transport model and complex bio-geo-chemical process to investigate the degradation of concrete material due to two major reactions: carbonation and Aggregate Silica Reaction(ASR). The chemical processes are simplified into a lookup table and cast into the transport model via source and sink term. The efficiency and robustness of the look-up table are further compared with a fully reactive transport model.

Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model for random variabilty of process parameters are formulated using BSIM and compared with the LUT model. The model was tested using a benchmark circuit. The maximum error in Monte Carlo simulation is found to be less than 3% for output current and less than 8% for output impedance.

This thesis aims to create effective and comprehensive learning materials for students enrolled in the Switching Theory and Digital Design course. The lab is designed to enable students to program an FPGA using VHDL in the Quartus programming environment to control traffic intersections with sensors and traffic signals. This laboratory aims to provide students with practical experience in digital engineering design and help them develop the necessary skills to program and implement state machines for regulating traffic environments