As time predictability is critical to hard real-time systems, it is not only necessary to accurately estimate the worst-case execution time (WCET) of the real-time tasks but also desirable to improve either the WCET of the tasks or time predictability of the system, because the real-time tasks with lower WCETs are easy to schedule and more likely to meat their deadlines. As a real-time system is an integration of software and hardware, the optimization can be achieved through two ways: software optimization and time-predictable architectural support. In terms of software optimization, we fi rst propose a loop-based instruction prefetching approach to further improve the WCET comparing with simple prefetching techniques such as Next-N-Line prefetching which can enhance both the average-case performance and the worst-case performance. Our prefetching approach can exploit the program controlow information to intelligently prefetch instructions that are most likely needed. Second, as inter-thread interferences in shared caches can signi cantly a ect the WCET of real-time tasks running on multicore processors, we study three multicore-aware code positioning methods to reduce the inter-core L2 cache interferences between co-running real-time threads. One strategy focuses on decreasing the longest WCET among the co-running threads, and two other methods aim at achieving fairness in terms of the amount or percentage of WCET reduction among co-running threads. In the aspect of time-predictable architectural support, we introduce the concept of architectural time predictability (ATP) to separate timing uncertainty concerns caused by hardware from software, which greatly facilitates the advancement of time-predictable processor design. We also propose a metric called Architectural Time-predictability Factor (ATF) to measure architectural time predictability quantitatively. Furthermore, while cache memories can generally improve average-case performance, they are harmful to time predictability and thus are not desirable for hard real-time and safety-critical systems. In contrast, Scratch-Pad Memories (SPMs) are time predictable, but they may lead to inferior performance. Guided by ATF, we propose and evaluate a variety of hybrid on-chip memory architectures to combine both caches and SPMs intelligently to achieve good time predictability and high performance. Detailed implementation and experimental results discussion are presented in this dissertation.

Real-time embedded systems (RTESs) have been widely used in modern society. And it is also very common to find them in safety and security critical applications, such as transportation and medical equipment. There are, usually, several constraints imposed on a RTES, for example, timing, resource, energy, and performance, which must be satisfied simultaneously. This makes the design of such systems a difficult problem. More recently, the security of RTESs emerges as a major design concern, as more and more attacks have been reported. However, RTES security, as a parameter to be considered during the design process, has been overlooked in the past. This thesis approaches the design of secure RTESs focusing on aspects that are particularly important in the context of RTES, such as communication confidentiality and side-channel attack resistance. Several techniques are presented in this thesis for designing secure RTESs, including hardware/software co-design techniques for communication confidentiality on distributed platforms, a global framework for secure multi-mode real-time systems, and a scheduling policy for thwarting differential power analysis attacks.  All the proposed solutions have been extensively evaluated in a large amount of experiments, including two real-life case studies, which demonstrate the efficiency of the presented techniques.

UAV (Unmanned Airborne Vehicle) is a source of entertainment and a pleasurable experience, attracting many young people to pursue it as a hobby. With the potential increase in the number of UAVs, the risk of using them for malicious purposes also increases. In addition, birds and UAVs have very similar maneuvers during flights. These UAVs can also carry a significant payload, which can have unintended consequences. Therefore, detecting UAVs near red-zone areas is an important problem. In addition, small UAVs can record video from large distances without being spotted by the naked eye. An appropriate network of sensors may be needed to foresee the arrival of such entities from a safe distance before they pose any danger to the surrounding areas. Despite the growing interest in UAV detection, limited research has been conducted in this area due to a lack of available data for model training. This thesis proposes a novel approach to address this challenge by leveraging experimental data collected in real-time using high-sensitivity sensors instead of relying solely on simulations. This approach allows for improved model accuracy and a better representation of the complex and dynamic environments in which UAVs operate, which are difficult to simulate accurately. The thesis further explores the application of machine learning and sensor fusion algorithms to detect UAVs and distinguish them from other objects, such as birds, in real-time. Specifically, the thesis utilizes YOLOv3 with deep sort and sensor fusion algorithms to achieve accurate UAV detection. In this study, we employed YOLOv3, a deep learning model known for its high efficiency and complexity, to facilitate real-time drone versus bird detection. To further enhance the reliability of the system, we incorporated sensor fusion, leading to a more stable and accurate real-time system, and mitigating the incidence of false detections. Our study indicates that the YOLOv3 model outperformed the state-of-the-art models in terms of both speed and robustness, achieving a high level of confidence with a score above 95%. Moreover, the YOLOv3 model demonstrated a promising capability in real-time drone versus bird detection, which suggests its potential for practical applications

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Due to close coupling to hardware and lack of software engineering technologies, the control software in digitally controlled power conversion systems is difficult to design and maintain. This is a natural consequence of a topology- or application-driven design approach. This research work proposes a distributed, modular, open control architecture for power conversion systems to reduce control design complexity, encapsulate and localize design dependencies, reduce unnecessary redesign effort and improve software quality. Dataflow style is chosen as the architectural style for the proposed control architecture based on comparative analysis. The detailed implementation of the dataflow architecture is presented. The resulting dataflow control software is evaluated in comparison to the legacy approach to control design used in industry and academia. The dataflow control software for a 3-phase voltage source inverter is also tested on a real PEBB-based converter system. To further explore the flexibility of control composition that is brought by the dataflow approach, the feasibility of dynamic control reconfiguration is also presented as an important future research direction. / Ph. D.

With ever increasing contents (safety, driver assistance, infotainment, etc.) in today's automotive systems that rely on electronics and software, the supporting architecture is integrated by a complex set of heterogeneous data networks. A modern automobile contains up to 100 ECUs and several heterogeneous communication buses (such as CAN, FlexRay, etc.), exchanging thousands of signals. The automotive Original Equipment Manufacturers (OEMs) and suppliers face a number of challenges such as reliability, safety and cost to incorporate the growing functionalities in vehicles. Additionally, reliability, safety and cost are major concerns for the industry. One of the important challenges in automotive design is the efficient and reliable transmission of signals over communication networks such as CAN and CAN-FD. With the growing features in automotives, the OEMs already face the challenge of saturation of bus bandwidth hindering the reliability of communication and the inclusion of additional features. In this dissertation, we study the problem of optimization of bandwidth utilization (BU) over CAN-FD networks. Signals are transmitted over the CAN/CAN-FD bus in entities called frames. The signal-to-frame-packing has been studied in the literature and it is compared to the bin packing problem which is known to be NP-hard. By carefully optimizing signal-to-frame packing, the CAN-FD BU can be reduced. In Chapter 3, we propose a method for offset assignment to signals and show its importance in improving BU. One of our contributions for an industrial setting is a modest improvement in BU of about 2.3%. Even with this modest improvement, the architecture's lifetime could potentially be extended by several product cycles, which may translate to saving millions of dollars for the OEM. Therefore, the optimization of signal-to-frame packing in CAN-FD is the major focus of this dissertation. Another challenge addressed in this dissertation is the reliable mapping of a task model onto a given architecture, such that the end-to-end latency requirements are satisfied. This avoids costly redesign and redevelopment due to system design errors. / Ph. D.

Energy consumption is increasingly affecting battery life and cooling for real- time systems. Dynamic Voltage and frequency Scaling (DVS) has been shown to substantially reduce the energy consumption of uniprocessor real-time systems. It is worthwhile to extend the efficient DVS scheduling algorithms to distributed system with dependent tasks. The dissertation describes how to extend several effective uniprocessor DVS schedul- ing algorithms to distributed system with dependent task set. Task assignment and deadline assignment heuristics are proposed and compared with existing heuristics concerning energy-conserving performance. An admission test and a deadline com- putation algorithm are presented in the dissertation for dynamic task set to accept the arriving task in a DVS scheduled real-time system. Simulations show that an effective distributed DVS scheduling is capable of saving as much as 89% of energy that would be consumed without using DVS scheduling. It is also shown that task assignment and deadline assignment affect the energy- conserving performance of DVS scheduling algorithms. For some aggressive DVS scheduling algorithms, however, the effect of task assignment is negligible. The ad- mission test accept over 80% of tasks that can be accepted by a non-DVS scheduler to a DVS scheduled real-time system.

SOFA-HI is an extension of the SOFA 2 component system,which is developed at Department of distributed and dependable systems. SOFA-HI focuses on support for development of real-time embedded applications using component-based approach. This thesis extends existing SOFA-HI implementation with support for development and deployment of SOFA-HI application to nxtOSEK platform which is a small-footprint real-time operating system and board support package for LEGO Mindstorms NXT. In particular, existing tools for application development and deployment are extended to support nxtOSEK platform. The thesis further provides pre-made components to allow communication with standard NXT sensors and actuators. Powered by TCPDF (www.tcpdf.org)

Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging and testing mechanisms, such as: single-step debugging, breakpoints setting and detection, monitoring, and modification of internal resources. However, the shortcoming of the conventional embedded in circuit emulator (EICE) is that the operation of the processor has to be suspended during debugging, which is categorized as static debugging (Static Debug) and is infeasible for real-time debugging. Therefore, this paper proposes a design alternative to support the real-time system debugging without suspending the microprocessor via the debug hardware Coprocessor14 (the Debug Coprocessor). In this paper, the embedded in circuit emulator is combined with Coprocessor 14 to provide both the static debugging and Run-time system debugging. After incorporating CP14 with the debugging mechanism, the control of the debug hardware is no longer limited to use the IEEE 1149.1 test port during debugging. On the other hand, the set of debugging constraints and the observation of the internal state of the microprocessor can be achieved by inserting the Coprocessor instruction at the program level.

Networked Control Systems (NCS) are distributed control systems where the sensor signals to the controllers and the control data to the actuators are enclosed in messages and sent over a communication network. On the one hand, the design of an NCS requires ensuring the stability of the control system and achieving system response that is as close as possible to that of an ideal system which demands network resources. On the other hand, these resources are limited and have to be allocated efficiently to accommodate for future system extensions as well as applications other than control purpose. Furthermore the NCS design parameters for the control system messages and the message transmission over the network are interdependent. In this thesis, we propose &ldquo / Integrated NCS Design (INtERCEDE: Integrated NEtwoRked Control systEm DEsign)&rdquo / a novel algorithmic approach for the design of NCS which ensures the stability of the control system, brings system response to that of an ideal system v as close as desired and conserves network bandwidth at the same time. The core of INtERCEDE is a bargaining game approach which iteratively calculates the message parameters and network service parameters. Our experimental results demonstrate the operation of INtERCEDE and how it computes the optimal design parameters for the example NCS.