This thesis explains the design, fabrication and characterization steps of a high dynamic range CMOS-MEMS capacitive accelerometer array and on-chip environmental sensors for bias drift compensation. Inertial navigation under harsh environments requires a high dynamic range accelerometer that can survive and provide continuous readout accuracy through shock events, while having a large dynamic range to capture fine-scale motions. The dynamic range target is set as 156 dB in accordance with navigation standard macro-electromechanical accelerometers, which corresponds to around 1 mG acceleration resolution in 50 kG input range. The small accelerometer cell design ensures shock survivability (e.g. up to 50 kG) by keeping the stress at the anchors below the fracture strength of thin-film oxide. Arraying multiple accelerometer cells in parallel lowers the fundamental thermomechanical noise limit set by the small mass of the individual accelerometer cells. Resonance frequency staggering between accelerometer cells suppresses ring-down oscillations. Parasitic capacitance of the high-impedance transduction signal is important to mitigate; undercut of the underlying silicon substrate and an aluminum etch of the top metal layer, incorporated in the CMOS-MEMS process flow, reduces the parasitic capacitance and improves sensitivity. PTAT temperature sensors, piezoresistive stress sensors and resonator-oscillators integrated across the accelerometer chip provide high-resolution environmental measurements for the compensation of long-term bias and scale factor drift. Simultaneous measurements from the accelerometer and environmental sensors demonstrate the correlation between environmental variations and long-term drift. Finite-element analysis shows that the scale factor stability of the accelerometer can be improved up to 1 ppm given the sensor array’s measurement resolution. The CMOS-MEMS accelerometer system-on-chip is fabricated in a TowerJazz 0.18 μm CMOS process. The post-CMOS MEMS processing steps are tuned to reduce the top metal milling and sidewall polymer deposition. A reactive ion etch recipe is developed for the removal of the top metal in order to reduce the parasitic capacitance and eliminate the risk of metal creep at spring beam anchors, thereby improve the bias stability. The PTAT temperature sensors have 3.1 mV/K measured sensitivity and 7.1 mK resolution with high repeatability. The compensation of the accelerometer readout for temperature variations down to 7.1 mK translates to 2.6 ppm scale factor stability for the accelerometer. The characterization of the stress sensors through the application of normal stress on the device package leads to an uncertainty in the amount of stress transferred to the stress sensors on the chip surface. The maximum measured stress sensitivity is 36.5 pV/Pa, which leads to 24.7 kPa stress resolution and translates to 1.7 ppm scale factor stability for the accelerometer without taking the stress attenuation into account. The measured sensitivity sets a lower bound on the sensitivity of the stress sensors implying that the stress resolution and the corresponding accelerometer scale factor stability is higher in practice. The measured frequency stability of the resonator-oscillator is 0.4 ppm, thereby the resonance frequency based variations of the accelerometer readout can be compensated to reach up to 0.8 ppm scale factor stability. However, the initial drift in the resonance frequency of the oscillators due to dielectric charging requires a long wait-time before these sensors can be used for accelerometer drift compensation. The accelerometer array is demonstrated to have 23.7 mG/√Hz noise floor and 70 mG bias stability. The maximum input acceleration applied on the device is limited to 4 kG by the split Hopkinson bar test setup. Improvement of the setup to transfer acceleration amplitudes up to 50 kG should validate the designed input range of the accelerometer array and lead to 117 dB dynamic range for the current design. The measurement bandwidth is fundamentally set by the 126 kHz resonance frequency of the accelerometer cells and can be further limited by filtering the readout signal to attenuate the transient oscillations faster. The nonlinearity of the accelerometer response is better than 1.2% in ±10 kG input range; however, it gets up to 19.0% in ±50 kG maximum input range. The long term bias drift of the accelerometer is shown to be correlated with the temperature and stress variations. Compensation of the accelerometer readout based on the stress and temperature sensor measurements leads to an observable improvement in the long term drift. However, the bias stability of the accelerometer is limited by excessive flicker noise in the system, which is believed to result from noise folding from higher frequencies. Suppression of the flicker noise in the system should allow for a more detailed study of the effect of environmental variations on the accelerometer readout and evaluation of more elaborate fitting algorithms for model based prediction and compensation of the bias drift to reach the target bias stability and dynamic range.

In this work the development of a Self-Powered System-On-Chip is explored by examining two components of process development in different perspectives. On one side, an energy component is approached from a biochemical standpoint where a Microbial Fuel Cell (MFC) is built with standard microfabrication techniques, displaying a novel electrode based on Carbon Nanotubes (CNTs). The fabrication process involves the formation of a micrometric chamber that hosts an enhanced CNT-based anode. Preliminary results are promising, showing a high current density (113.6mA/m2) compared with other similar cells. Nevertheless many improvements can be done to the main design and further characterization of the anode will give a more complete understanding and bring the device closer to a practical implementation. On a second point of view, nano-patterning through silicon nitride spacer width control is developed, aimed at producing alternative sub-100nm device fabrication with the potential of further scaling thanks to nanowire based structures. These nanostructures are formed from a nano-pattern template, by using a bottom-up fabrication scheme. Uniformity and scalability of the process are demonstrated and its potential described. An estimated area of 0.120μm2 for a 6T-SRAM (Static Random Access Memory) bitcell (6 devices) can be achieved. In summary, by using a novel sustainable energy component and scalable nano-patterning for logic and computing module, this work has successfully collected the essential base knowledge and joined two different elements that synergistically will contribute for the future implementation of a Self-Powered System-on-Chip.

Among many which are placed on modern embedded systems is also the need of storing multiple system boot image versions and the ability to select from them upon boot time, depending on a function which they provide. This thesis describes the development of a system update application for Xilinx Zynq-7000 devices. The application includes a simple embedded HTTP server for a remote file transfer. A client is allowed to upload the boot image file with the system update from either command line application or using the web page developed for this purpose.

Traditional design methods could not cope with the recent development of multiprocessorsystems-on-chip (MPSoC). Especially, hard real-time systems that requiretime-predictability are cumbersome to develop. What is needed, is an efficient, automaticprocess that abstracts away all the implementation details. ForSyDe, a designmethodology developed at KTH, allows this on the system modelling side. The NoCSystem Generator, another project at KTH, has the ability to create automaticallycomplex systems-on-chip based on a network-on-chip on an FPGA. Both of themsupport the synchronous model of computation to ensure time-predictability. Inthis thesis, these two projects are analysed and modelled. Considering the characteristicsof the projects and exploiting the properties of the synchronous model ofcomputation, a mapping process to map processes to the processors at the differentnetwork nodes of the generated system-on-chip was developed. The mapping processis split into three steps: (1) Binding processes to processors, (2) Placement of theprocessors on net network nodes, and (3) scheduling of the processes on the nodes.An implementation of the mapping process is described and some synthetic exampleswere mapped to show the feasibility of algorithms.

The continual increase of wireless technologies in the world has motivated the use of phased arrays to mitigate radio frequency interference (RFI). There are many methods of performing beamforming for RFI rejection, but they are traditionally physically large and complicated solutions. Phased arrays need to be shrunk and made cheaper for them to see widespread use. This work presents several compact phased array receivers for different applications. The first part of this thesis presents a software GPS processor for a digital beamforming GPS receiver. The receiver is small enough to be flown on drones and enables GPS signals to be processed and a user’s position to be determined. Using digital beamforming, it can operate even under poor conditions such as intentional jamming, RFI, and large multipath effects. Next, this work builds a frontend RF chain for a true time delay phased array receiver. The receiver uses analog true delay delay chips to mitigate radio frequency interference in sensitive instruments. True time delay allows for analog beamforming over a wide bandwidth, but compact true time delay solutions are new and untested. The receiver allows these solutions to be properly vetted in a full system. The chain uses novel compact wideband antennas for L-band frequencies and traditional low cost amplifiers and filters. The last section of this thesis updates the open-source CASPER project to fully support RF system-on-chips. CASPER is an open-source framework for radio astronomy instruments. It speeds up the design and implementation of radio astronomy instruments on compact platforms and makes them easier to interact with. This work expands the framework to use the transmit abilities of advanced RF system-on-chip platforms. With this expansion, full duplex systems such as communications and radar can now also use CASPER. A full loopback beamforming test built on CASPER demonstrates both transmit and receive beamforming.

El sistema neurorregulador en los humanos es un sistema nervioso complejo que consta de un grupo heterogéneo de centros nerviosos. Estos centros están distribuidos a lo largo de la médula espinal, actúan de forma autónoma, se comunican mediante interconexiones nerviosas, gobiernan y regulan el comportamiento de órganos y sistemas en los seres humanos. A partir del estudio del funcionamiento y composición del sistema neurorregulador del tracto urinario inferior (LUT), se ha conseguido aislar los centros que intervienen en su comportamiento. El objetivo es comprender el funcionamiento individual de cada centro para crear un modelo general del sistema neurorregulador capaz de operar a nivel de centro nervioso. El modelo creado se basa en la teoría de los sistemas multiagente (MAS) basados en agentes con capacidad de percibir, deliberar y ejecutar (agentes PDE). En nuestro modelo, cada agente representa el comportamiento de un centro nervioso. La propuesta supone un avance con respecto a los modelos existentes, que al no permitir la intervención a nivel de los elementos que componen el sistema, ni tratar aspectos como, por ejemplo, disfunciones, de forma independiente o aislada, son modelos de caja negra. A partir del estudio realizado a lo largo de los últimos veinte años y del modelo MAS definido, en esta investigación se propone como objetivo la propuesta de un modelo de centro nervioso para el diseño System on Chip (SoC) de un procesador con la estructura de un agente PDE capaz de desempeñar las funciones de un centro nervioso del sistema neurorregulador en los humanos: en concreto, del centro nervioso córtico-diencefálico. Esta propuesta se caracteriza porque el funcionamiento del centro es totalmente configurable y programable, con la idea de que el diseño propuesto pueda ser válido para otros centros que componen el sistema neurorregulador. Esta investigación supone un nuevo paso adelante en nuestro objetivo de crear un chip parametrizable, capaz de desarrollar cualquier función neurorreguladora, implantable en el cuerpo y con capacidad para operar de forma coordinada con el sistema neurorregulador biológico. En esta memoria se presenta de forma cronológica el proceso de la investigación junto con sus principales logros: un modelo formal del centro nervioso córtico-diencefálico, el diseño en hardware de un procesador de centro nerviosos parametrizable, un prototipo sobre tecnología en hardware reconfigurable (FPGA) de este diseño, un entorno de pruebas y simulación para la evaluación de la propuesta y, finalmente, el análisis de los resultados obtenidos y la comparación de su comportamiento con el de los datos obtenidos a partir de pacientes reales, observando que se ajusta al esperado en un ser humano. Por lo tanto, los resultados obtenidos avalan ampliamente la validez de la propuesta realizada, ya que muestran que los sistemas obtenidos son capaces de desplegar los comportamientos para los que fueron diseñados originalmente pero que, además, es posible su rápida adaptación, modificación, actualización, automatización y absorción de nuevas tecnologías y nuevo conocimiento.

Cyber-security is now a critical concern in a wide range of embedded computing modules, communications systems, and connected devices. These devices are used in medical electronics, automotive systems, power grid systems, robotics, and avionics. The general consensus today is that conventional approaches and software-only schemes are not sufficient to provide desired security protections and trustworthiness. Comprehensive hardware-software security solutions so far have remained elusive. One major challenge is that in current system-on-chip (SoCs) designs, processing elements (PEs) and executable codes with varying levels of trust, are all integrated on the same computing platform to share resources. This interdependency of modules creates a fertile attack ground and represents the Achilles’ heel of heterogeneous SoC architectures. The salient research question addressed in this dissertation is “can one design a secure computer system out of non-secure or untrusted computing IP components and cores?”. In response to this question, we establish a generalized, user/designer-centric set of design principles which intend to advance the construction of secure heterogeneous multi-core computing systems. We develop algorithms, models of computation, and hardware security primitives to integrate secure and non-secure processing elements into the same chip design while aiming for: (a) maintaining individual core’s security; (b) preventing data leakage and corruption; (c) promoting data and resource sharing among the cores; and (d) tolerating malicious behaviors from untrusted processing elements and software applications. The key contributions of this thesis are: 1. The introduction of a new architectural model for integrating processing elements with different security and trust levels, i.e., secure and non-secure cores with trusted and untrusted provenances; 2. A generalized process isolation design methodology for the new architecture model that covers both the software and hardware layers to (i) create hardware-assisted virtual logical zones, and (ii) perform both static and runtime security, privilege level and trust authentication checks; 3. A set of secure protocols and hardware root-of-trust (RoT) primitives to support the process isolation design and to provide the following functionalities: (i) hardware immutable identities – using physical unclonable functions, (ii) core hijacking and impersonation resistance – through a blind signature scheme, (iii) threshold-based data access control – with a robust and adaptive secure secret sharing algorithm, (iv) privacy-preserving authorization verification – by proposing a group anonymous authentication algorithm, and (v) denial of resource or denial of service attack avoidance – by developing an interconnect network routing algorithm and a memory access mechanism according to user-defined security policies. 4. An evaluation of the security of the proposed hardware primitives in the post-quantum era, and possible extensions and algorithmic modifications for their post-quantum resistance. In this dissertation, we advance the practicality of secure-by-construction methodologies in SoC architecture design. The methodology allows for the use of unsecured or untrusted processing elements in the construction of these secure architectures and tries to extend their effectiveness into the post-quantum computing era.

Les réseaux de capteurs sans-fil sont une nouvelle technologie qui permet de déployer des capteurs hétérogènes et de les faire communiquer sans fil et de façon autonome. Cette capacité nouvelle à surveiller ou instrumenter le monde qui nous entoure ouvre la voie à de nouvelles applications innovantes ou à une évolution majeure d’applications déjà existantes.D’une dizaine de nœuds à plusieurs milliers, les réseaux de capteurs sans fil commencent à conquérir le monde industriel et notre vie quotidienne. Leurs besoins en communications, gestion, génération et stockage de l’énergie, miniaturisation et réduction des coûts ne nécessitent pas seulement de perfectionner les technologies actuelles mais bien d’en inventer de nouvelles. Parmi toutes les applications révolutionnaires des réseaux de capteurs sans fil comme dans la santé, l’environnement, l’industrie et le militaire, l’une des applications les plus transformatrices est la surveillance de structure. La surveillance de structure est l’art de surveiller tout ce qui peut s’abimer, s’user ou tomber en panne. Elle est particulièrement importante dans les domaines des transports et du bâtiment, étant donné que la sécurité des personnes est en jeu. En plaçant aux endroits stratégiques des capteurs sans-fil, il sera possible de prévoir et de prévenir la défaillance d’un pont, l’usure d’un avion ou d’un train ou la déformation d’un bâtiment. La surveillance de structure permet de prévenir les pannes et les défaillances, de réduire les coûts de maintenance et d’améliorer les performances. C’est un processus complexe qui implique plusieurs technologies : des capteurs, la transmission de l’information et l’analyse des données. La nature (accéléromètre, gyroscope, jauge de contrainte, température, pression, fuite, givre, etc. . .), la position ainsi que le nombre de capteurs sont dictés et dépendants des besoins de l’analyse de la structure qui doit être effectuée. De ce fait, les contraintes imposées au système de transmission de données sans fil, afin d’offrir une couverture suffisante de la structure de l’appareil avec plusieurs centaines voire plusieurs milliers de capteurs que leur localisation rendra difficile d’accès, nécessitent des nouvelles innovations en matière d’efficacité énergétique et de performance de communication. Ce travail s’intéresse à la conception et l’implémentation d’un système de transmission de données dans un réseau de capteurs sans-fil. Après une présentation des exigences du système de surveillance de structure aéronautique, l’architecture générale du système de surveillance est décrite. Une couche physique spécifique à haute efficacité énergétique basée sur l’Impulse-Radio UltraWide Band a été conçue. Les designs complets de l’émetteur et du récepteur IR-UWB sont présentés ainsi que l'optimisation du codage canal par rapport à la consommation énergétique. Une couche MAC spécifique permettant un nombre important de nœuds et une efficacité énergétique élevée basée sur du TDMA reconfigurable a été conçue. Plusieurs prototypes ont été implémentés pour valider la conception et démontrer les performances. Ces implémentation utilise des techniques avancées d’optimisation de la consommation énergétique et de reconfigurabilité afin de répondre aux exigences des réseaux de capteurs sans-fil. Des simulations ASIC permettent également de prévoir que ce système permettra de supporter des débits applicatifs de plusieurs centaines de mégabits par seconde, tout en permettant à plusieurs dizaines de nœuds de communiquer. Les performances énergétiques de ce système de communication sont aujourd’hui à l’état de l’art. Enfin, cette technologie de communication sans-fil a été intégrée dans un système complet de deux nœuds capteurs et d’un routeur dans un démonstrateur FPGA / Wireless Sensor Networks (WSN) is an emerging technology which allows deploying wireless communicating autonomous heterogenous sensors. This monitoring capability paves the way for new innovative applications or breakthrough evolution of existing ones. WSN have started to change the industry and our daily lives. Their communication, energy, miniaturization and cost requirements cannot be met by evolutions of current technologies but will require new innovations.Among health, environment, industrial and military applications for WSN, one of the most revolutionary is Structural Health Monitoring (SHM). SHM is the art of monitoring anything which can wear, break down or be damaged. It is of utmost importance in safety sensitive domains such as the transport and construction industries.By placing sensors in carefully chosen locations, SHM will allow failure prediction, cost reduction and improved performance of bridges, planes, building or engines.The tens to thousands of sensors and the huge amount of data generated places a strong burden on the wireless communication of the nodes, which cannot be satisfied with today’s technology. This work presents the design and implementation works such a wireless communication system.Following a presentation of the context and requirement of this work, a general description of the SHM system is given. A specific highly energy efficient physical layer based on Impulse-Radio UltraWide Band (IR-UWB) has been designed.The complete IR-UWB transmitter and receiver are detailed, including the energy efficiency optimized channel coding. A specific Medium Access Control (MAC) layer allowing a large number of communicating nodes based on reconfigurableTime Division Multiple Access (TDMA) was designed. Several prototypes of this system have been implemented to prove feasibility and performance. These implementations employ advanced energy consumption reduction and reconfigurability techniques to answer WSN communication challenges. An ASIC implementation simulation has demonstrated hundreds of megabits per second data rate at state of the art energy efficiency

No description available.

Yes / The antenna array designed to operate over 0.450-0.475 Terahertz comprises two dielectric resonators (DRs) that are stacked vertically on top of each other and placed on the surface of the slot antenna fabricated on a silicon substrate using standard CMOS technology. The slot created in the silicon substrate is meandering and is surrounded by metallic via-wall to prevent energy dissipation. The antenna has a maximum gain of 4.5dBi and radiation efficiency of 45.7% at 0.4625 THz. The combination of slot and vias transform the antenna to a metamaterial structure that provides a relatively small antenna footprint. The proposed series-fed double DRs on-chip antenna array is useful for applications in THz integrated circuits. / Partially supported by innovation programme under grant agreement H2020-MSCA-ITN-2016 SECRET-722424 and the financial support from the UK Engineering and Physical Sciences Research Council (EPSRC) under grant EP/E0/22936/1.