Smartphone/tablet Systems-on-Chip (SoCs) integrate increasing number of components to offer more functionality. Capacity and efficiency of data communication between memory and other hardware blocks have become a major concern in the SoC design. To address this concern, we propose to use Network-on-Chip (NoC) architectures, to meet high bandwidth, and low power and area demands. We propose a Quality-of-Service (QoS) scheme to differentially provision network resources to cater to different performance requirements by different hardware blocks. Implementation and evaluation are performed on a simulation infrastructure we construct specifically for this type of SoCs. We demonstrate, via simulation results, that the proposed Dynamic QoS schemes can achieve better bandwidth provisioning, with good area and power efficiencies.

As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck in large-scale multicore systems. In designing efficient input buffers of NoC routers for better performance and power efficiency, Spin-Torque Transfer Magnetic RAM (STT-MRAM) is regarded as a promising solution due to its nature of high density and near-zero leakage power. Previous work that adopts STT-MRAM in designing NoC router input buffer shows a limitation in minimizing the overhead of power consumption, even though it succeeds to some degree in achieving high network throughput by the use of SRAM to hide the long write latency of STT-MRAM. In this thesis, we propose a novel input buffer design that depends solely on STT-MRAM without the need of SRAM to maximize the benefits of low leakage power and area efficiency inherent in STT-MRAM. In addition, we introduce power-efficient buffer refreshing schemes synergized with age-based switch arbitration that gives higher priority to older flits to remove unnecessary refreshing operations. On an average, we observed throughput improvements of 16% on synthetic workloads and benchmarks.

This thesis was on the development of a high-throughput electrokinetically-controlled heterogeneous immunoassay (EK-IA) microfluidic chip for clinical application. Through a series of experimental studies, a high-throughput EK-IA was developed. This EK-IA was capable of automatically screening multiple analytes from up to 10 samples in parallel, in only 26 min. Flow control in an integrated microfluidic network was realized by numerical simulation of the transport processes. This EK-IA was successfully applied to detect E. coli O157:H7 antibody and H. pylori antibody from human sera with satisfactory accuracy. Simultaneous screening of both antibodies from human sera was also achieved, demonstrating the potential of this EK-IA for efficiently detecting multiple pathogenic infections in clinical settings. Preliminary work on the application of EK-IA to detect biomarkers of embryo development in embryo culture media also yielded good results. In addition to the experimental studies, the reaction kinetics of this microfluidic EK-IA has also been investigated, using both numerical simulation and a modified Damköhler number. Targeted towards a more sensitive assay, the influences of several important parameters on the reaction kinetics were studied. This EK-IA holds great promise for automated and high-throughput immunoassay in clinical environments.

This thesis outlines the fabrication of two atom chips for the study of interactions between ⁸⁷Rb Rydberg atoms and a Au surface. Atom chips yield tightly confined, cold samples of an atomic species by generating magnetic fields with high gradients using microfabricated current-carrying wires. These ground state atoms may in turn be excited to Rydberg states. The trapping wires of Chip 1 are fabricated using thermally evaporated Cr/Au and patterned using lift-off photolithography. Chip 2 uses a Ti/Pd/Au tri-layer, instead of Cr/Au, to minimize interdiffusion. The chip has a thermally evaporated Au surface layer for Rydberg atom-surface interactions, which is separated from the underlying trapping wires by a planarizing polyimide dielectric. The polyimide was patterned using reactive ion etching. Special attention was paid to the edge roughness and electrical properties of the trapping wires, the planarization of the polyimide, and the grain structure of the Au surface.

The deep sub micron process technology and application convergence increases the design challenges in System-on-Chip (SoC). The traditional bus based on chip communication are not scalable and fails to deliver the performance requirements of the complex SoC. The Network on Chip (NoC) has been emerged as a solution to address these complexities of a efficient, high performance, scalable SoC design. The Aethereal NoC provides the latency and throughput bounds by pipelined timedivision multiplexed (TDM) circuit switching architecture. A global synchronous clock defines the timing for TDM, which is not beneficial for decreasing process geometry and increasing clock frequency. This thesis work focuses on the Aelite NoC architecture. The Aelite NoC offering guaranteed services exploits the complexities of System-on-Chip design with real time requirements. The Aelite NoC implements flit synchronous communication using mesochronous and asynchronous links.

Many applications for the analysis and processing of biological materials require the enrichment of cell subpopulations. Conventional cell sorting systems are large and expensive with complex equipment that necessitates specialized personnel for operation. Employing microfluidics technology for lab-on-a-chip adaptation of these devices provides several benefits: improved transport control, reduced sample volumes, simplicity of operation, portability, greater accessibility, and reduced cost. The designs of microfluidic cell sorting chips vary widely in literature; evaluation and optimization efforts are rarely reported. This study intends to investigate the primary components of the design to understand the effect of various parameters and to improve the performance of the microfluidic chip. Optimized individual elements are incorporated into a proposed cell sorter chip with the ability to dynamically sort target cells from a non-homogeneous solution using electrical driving forces. Numerical and experimental results are used to evaluate the sample focusing element for controlled cell dispensing, the sorting configuration for target cell collection, and the flow elements for reduced pressure effects and prevention of flow blockages. Compact models are adapted to solve the potential field and flow field in the chip and to predict the focused sample stream width. A commercial CFD package is used to perform 2-D simulations of the potential, velocity, and concentration fields. A fluorescence microscopy visualization system is implemented to conduct experiments on several generations of chip designs. The data from sample focusing experiments, performed with fluorescent dye samples, is analyzed using a Gaussian distribution model proposed in this work. A technique for real-time monitoring of fluorescent microspheres in the microfluidic chip enables the use of dynamic cell sorting to emulate fully autonomous operation. The performance values obtained from these experiments are used to characterize the various design configurations. Sample focusing is shown to depend largely on the relative size of the sheath fluid channel and the sample channel, but is virtually independent of the junction shape. Savings in the applied potential can be achieved by utilizing the size dependency. The focusing performance also provides information for optimizing the widths of the channels relative to the cell size. Successful sorting of desired cells is demonstrated for several designs. Key parameters that affect the sorting performance are discussed; a design employing the use of supplemental fluid streams to direct the particle during collection is chosen due to a high sorting evaluation and a low sensitivity to flow anomalies. The necessary reduction of pressure influences to achieve reliable flow conditions is accomplished by introducing channel constrictions to increase the hydrodynamic resistance. Also, prolonged operation is realized by including particle filters in the proposed design to prevent blockages caused by the accumulation of larger particles. A greater understanding of the behaviour of various components is demonstrated and a design is presented that incorporates the elements with the best performance. The capability of the microfluidic chip is summarized based on experimental results of the tested designs and theoretical cell sorting relationships. Adaptation of this chip to a stand-alone, autonomous device can be accomplished by integrating an optical detection system and further miniaturization of the critical components.

This thesis outlines the fabrication of two atom chips for the study of interactions between ⁸⁷Rb Rydberg atoms and a Au surface. Atom chips yield tightly confined, cold samples of an atomic species by generating magnetic fields with high gradients using microfabricated current-carrying wires. These ground state atoms may in turn be excited to Rydberg states. The trapping wires of Chip 1 are fabricated using thermally evaporated Cr/Au and patterned using lift-off photolithography. Chip 2 uses a Ti/Pd/Au tri-layer, instead of Cr/Au, to minimize interdiffusion. The chip has a thermally evaporated Au surface layer for Rydberg atom-surface interactions, which is separated from the underlying trapping wires by a planarizing polyimide dielectric. The polyimide was patterned using reactive ion etching. Special attention was paid to the edge roughness and electrical properties of the trapping wires, the planarization of the polyimide, and the grain structure of the Au surface.

This thesis presents a link-level latency analysis for real-time network-on-chip interconnects that use priority-based wormhole switching. This analysis incorporates both direct and indirect interferences from other traffic flows, and it leverages pipelining and parallel transmission of data across the links. The resulting link-level analysis provides a tighter worst-case upper-bound than existing techniques, which we verify with our analysis and simulation experiments. Our experiments show that on average, link-level analysis reduces the worst-case latency by 28.8%, and improves the number of flows that are schedulable by 13.2% when compared to previous work.

Traditionally, the microprocessor design has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip continues to increase, the design of communication architecture has become a crucial and dominating factor in defining performance models of the overall system. On-chip networks, also known as Networks-on-Chip (NoC), emerged recently as a promising architecture to coordinate chip-wide communication. Although there are numerous interconnection network studies in an inter-chip environment, an intra-chip network design poses a number of substantial challenges to this well-established interconnection network field. This research investigates designs and applications of on-chip interconnection network in next-generation microprocessors for optimizing performance, power consumption, and area cost. First, we present domain-specific NoC designs targeted to large-scale and wire-delay dominated L2 cache systems. The domain-specifically designed interconnect shows 38% performance improvement and uses only 12% of the mesh-based interconnect. Then, we present a methodology of communication characterization in parallel programs and application of characterization results to long-channel reconfiguration. Reconfigured long channels suited to communication patterns enhance the latency of the mesh network by 16% and 14% in 16-core and 64-core systems, respectively. Finally, we discuss an adaptive data compression technique that builds a network-wide frequent value pattern map and reduces the packet size. In two examined multi-core systems, cache traffic has 69% compressibility and shows high value sharing among flows. Compression-enabled NoC improves the latency by up to 63% and saves energy consumption by up to 12%.

As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC) implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC) architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. The processing elements (PEs) communicate with each other by exchanging messages over the network and these messages go through buffers in each router. Buffers are one of the major resource used by the routers in virtual channel flow control. In this thesis, we analyze two kinds of buffer allocation approaches, static and dynamic buffer allocations. These approaches aim to increase throughput and minimize latency by means of virtual channel flow control. In statically allocated buffer architecture, size and organization are design time decisions and thus, do not perform optimally for all traffic conditions. In addition, statically allocated virtual channel consumes a waste of area and significant leakage power. However, dynamic buffer allocation scheme claims that buffer utilization can be increased using dynamic virtual channels. Dynamic virtual channel regulator (ViChaR), have been proposed to use centralized buffer architecture which dynamically allocates virtual channels and buffer slots in real-time depending on traffic conditions. This ViChaR’s dynamic buffer management scheme increases buffer utilization, but it also increases design complexity. In this research, we reexamine performance, power consumption, and area of ViChaR’s buffer architecture through implementation. We implement a generic router and a ViChaR architecture using Verilog-HDL. These RTL codes are verified by dynamic simulation, and synthesized by Design Compiler to get area and power consumption. In addition, we get latency through Static Timing Analysis. The results show that a ViChaR’s dynamic buffer management scheme increases the latency and power consumption significantly even though it could increase buffer utilization. Therefore, we need a novel design to achieve high buffer utilization without a loss.