Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

The field of chip design is characterized by contradictory pressures to reduce time-to-market and maintain a high level of reliability. As a result, module reuse has become common practice in chip design. To save time on both design and verification, Systems-on-Chips (SoCs) are composed using pre-designed and pre-verified modules. The integrated modules are often designed by different groups and for different purposes, and are later integrated into a single chip. In the absence of a single interface standard for such modules, "plug-n-play" style integration is not likely, as the subject modules are often designed to comply with different interface protocols. For such modules to communicate correctly there is a need for some glue logic, also called a protocol converter that mediates between them. Though much research has been dedicated to the protocol converter synthesis problem of SoC communication, converter synthesis is still performed manually, consuming development and verification time and risking human error. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the Hardware Description Language (HDL) implementation level or grossly simplify the structure of the protocols considered. This thesis develops and presents techniques for automatic synthesis of provably correct on-chip protocol converters. Basing the solution on a formal approach, a novel state-machine based formalism is presented for modelling bus-based protocols and formalizing the notions of protocol compatibility and correct protocol conversion. Algorithms for automatic compatibility checking and provably-correct converter synthesis are derived from the formalism, including a systematic exploration of the design space of the protocol converter, the first in the field, which enables generation of various alternative deterministic converters. The work presented is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modelling of protocol characteristics and automatic translation of the constructed converter to HDL.

The field of chip design is characterized by contradictory pressures to reduce time-to-market and maintain a high level of reliability. As a result, module reuse has become common practice in chip design. To save time on both design and verification, Systems-on-Chips (SoCs) are composed using pre-designed and pre-verified modules. The integrated modules are often designed by different groups and for different purposes, and are later integrated into a single chip. In the absence of a single interface standard for such modules, "plug-n-play" style integration is not likely, as the subject modules are often designed to comply with different interface protocols. For such modules to communicate correctly there is a need for some glue logic, also called a protocol converter that mediates between them. Though much research has been dedicated to the protocol converter synthesis problem of SoC communication, converter synthesis is still performed manually, consuming development and verification time and risking human error. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the Hardware Description Language (HDL) implementation level or grossly simplify the structure of the protocols considered. This thesis develops and presents techniques for automatic synthesis of provably correct on-chip protocol converters. Basing the solution on a formal approach, a novel state-machine based formalism is presented for modelling bus-based protocols and formalizing the notions of protocol compatibility and correct protocol conversion. Algorithms for automatic compatibility checking and provably-correct converter synthesis are derived from the formalism, including a systematic exploration of the design space of the protocol converter, the first in the field, which enables generation of various alternative deterministic converters. The work presented is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modelling of protocol characteristics and automatic translation of the constructed converter to HDL.

Real-time image processing requires not only sophisticated heuristic algorithms customized for a particular application, but also needs substantial computational power to handle a massive quantity of input image data. Reconfigurable System-on- Chip (rSoC), a powerful method to harness the power of FPGA technology, is well suited to real-time image processing. It balances the design cost and performance via a combination of hardware and software. However, hardware/software co-design requires specialized design skills, and designs are complex. This thesis investigates how best to use FPGA-based reconfigurable computing to provide efficient speed-up of real-time image processing algorithms. Existing rSoC systems, face detection and recognition algorithms, hardware/software co-design methods are first reviewed and analyzed. The advantages and disadvantages of existing research results are also presented. However, these existing approaches all have shortcomings. A new rSoC system without a separate host machine is presented for standalone embedded platforms. A new hardware/software co-design method including hardware/software communication and partitioning is also explained. This rSoC system is a highly modular system, it runs without a host machine and it supports the Linux operating systems. Hardware and software designs can be rapidly implemented on this new platform. A new method for hardware/software communication in rSoC design is presented, which is based on shared memory and semaphores, and makes hardware coprocessors appear like software processes. Individual processes in hardware-software systems can communicate without knowing whether other co-operating processes are hardware or software. This approach enables re-useable hardware components to be readily accessed by designers, without specialist hardware knowledge. Processes also can be easily swapped between hardware and software. The partitioning method handles the software/hardware partition iteratively during the implementation. The partition is based on experimental profiling, so it is easier to realize and may achieve a more optimal result than a fixed a priori partition. An example face recognition system has been implemented to test the new design method. It is a four-stage pipeline architecture which contains image capture, face detection, image enhancement, and face recognition. Firstly, a software-only solution using semaphores and shared memory method is implemented on a Linux PC. Results of 5.5 frames per second indicate that the speed may not be fast enough for real-time image processing. Secondly, that software-only solution is moved to the new rSoC platform. The performance of 0.1 frames per second is worse than PC platform since the PC’s CPU is much more powerful than the rSoC’s. Finally the new design method is used to move some bottleneck modules to hardware. The new hardware/software communication method is used, so software modules remain unchanged and unaware of the movement of other modules to hardware. Results show that moving only one module to hardware was not helpful. However when both the bottleneck modules were moved to hardware, the system speedup was approximately 200 with a final system speed of 19 frames per second.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Techn. University, Diss., 2007--Darmstadt.

Zugl.: Kaiserslautern, Techn. Univ., Diss., 2006

Stuttgart, Univ., Diss., 2007.

Stuttgart, Univ., Diss., 2008.

Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2008/07/23). Includes bibliographical references.