This thesis is concerned with cutting farm machine and it consists of three parts. Theoretical part describes mechanism of chip formation, shape of the chips, temperature of the chips, technological variables describing chips, chip conveyor, chip crusher, briquetting press and coolant filter. In the next part there is proposal of design of cutting farm machine for production cell consists of six machining center. At last part there is design proposal and calculation of chip conveyor.

archives@tulane.edu / Fibrotic diseases comprise up to 45% of deaths in the industrialized world. Few effective anti-fibrotic therapeutics exist, due in part to the lack of human-relevant preclinical models. The goal of this research was to improve the modeling of fibrotic diseases in microphysiological systems (MPS) by engineering quiescence in cultured human fibroblasts prior to MPS incorporation. To create an assay for testing this approach, a versatile organ chip was designed while optimizing workflow for production of the organ chip molds with an SLA 3D printer. After identifying 2D culture conditions that repress fibroblast activation, we tested the hypothesis that the 2D culture protocol would impact the fibrotic baseline in our MPS. 3D confocal microscopy and multi-metric image analysis of immunostaining for cellular and extracellular matrix (ECM) components via intensity and pattern quantification revealed the establishment of more physiological baseline for MPS fibrosis models. To test in a disease-relevant context, we created a model of the stromal reaction in lung cancer using our organ chip and demonstrated that our integrated MPS can be used to quantify the fibrosis-inducing effects of cancer cells that drive stromal reactions. / 1 / Max Wendell

archives@tulane.edu / The goal of this research was to establish a novel digital manufacturing-based workflow for the fabrication of membrane free organ chip (MFOC) systems. This workflow is based on the implementation of top-down design, starting with CAD design of molds for MFOC components and can be conducted on a benchtop removing the need for cleanroom use. In conducting this research, a commercially available SLA printer was characterized and optimized for manufacturing molds suitable for MFOC fabrication. To achieve this, extensive research was required to determine printer resolution limits and work within the limitations of the resins available for printing. Specifically, the molds need to be flat and smooth in order to produce perfectly horizontal and transparent PDMS devices. Post-processing workflows were engineered to satisfy these MFOC design constraints. After establishing a reliable and reproducible workflow for MFOC fabrication, the focus of the research was reduction to practice, i.e. achieving a design that enables loading MFOC with patterned aqueous solutions with 100% success and a high degree of forgiveness. Key MFOC dimensions were systematically varied in a manner only possible with the rapid prototyping capability of DM in a series of experiments with a standardized injection test and success rate of loading as the primary output. With a robust MFOC design in place, more complex designs for tissue patterning applications were created, and advanced configurations for engineering patterned vascularized stromal tissues were tested and validated. Seqeuntial and simultaneous loading scenerios were imvestigated to better understand cell migration impedence in multi-gel lane devices. / 1 / William Bralower

We study two deterministic analogues of random walks. The first is the chip-firing game, a single player game played by moving chips around a directed graph, popularised by Björner and Lovász. We find an efficient simulation of boolean circuits and Turing machines using instances of the chip-firing game - after assigning a fixed strategy to the player. The second is the Propp machine, or the rotor router model, a quasirandom model intro- duced by Priezzhev. We improve results of Kijima et al. and show a bound of O(m) on the discrepancy of this process from a random walk on d-regular graphs with m edges. 1

Electromagnetic waves in the terahertz spectral range have gained significant research focus due to their applications in various fields of science. To effectively generate and integrate terahertz waves in systems, appropriate waveguide design is critical. Conventionally waveguides have been used to control the propagation of electromagnetic waves. A waveguide with low loss and dispersion is always preferred. But achieving these characteristics is quite challenging especially if operating in the terahertz spectral range. There are inherent material and geometric limitations that exist for terahertz waveguides. It is therefore important to optimize the design to enable their use in applications efficiently. This thesis investigates the characteristics of three primary terahertz waveguides based on the underlying theory and results obtained from simulations. The three waveguides are parallel-plate waveguides, two-wire waveguides, and coplanar striplines. The work in this thesis mostly focuses on coplanar striplines, optimal for building a highly efficient commercial and portable terahertz system-on-chip (TSOC). The contribution of the thesis is around the use of different types of passive components mounted on a thin commercial Silicon Nitride membrane. A bias tee is introduced which is a combination of interdigitated electrodes and a meander inductor. The length of the interdigitated electrodes and the gap between them are 55 um and 5 um, respectively. The S21 parameter for this structure ranges from -24 dB/mm at near-zero frequencies to -0.8 dB/mm at 1 THz. This indicates that the designed bias tee can appropriately block low frequencies. Split-ring resonators are also used to act as band-stop filters. The resonant frequency of the resonator depends on the radii of the split-rings. In the optimized design, the internal radius of the outer ring is 25 um and the external radius of the inner ring is 20 um. This results in a narrowband band-stop filter with its resonant frequency centered at 701 GHz. The optimized final TSOC design discussed in this work uses these passive components placed on the Silicon Nitride membrane and is shown to have a total loss that is 3 dB/mm less than any of the previous work for terahertz frequencies. / Graduate

Chip Multi-Processor (CMP) platforms, well-established in the server, desktop and embedded domain, succeeded in overcoming the power consumption and heat dissipation bottlenecks by integrating multiple cores, less complex and powerful than their single-core ancestors, in a single die. A major issue induced by the design of the CMPs is contention for the shared resources of the platform, Last Level Cache (LLC) and main memory bandwidth. Applications, running concurrently on the cores, compete with each other for the shared resources, and are subject to performance degradation. The way applications are assigned to the CMP, is crucial for the overall performance of the system. A scheduling policy that accounts for contention will bring high performance speed-ups, whereas an agnostic one will generate unpredictable contention conditions. For this reason the significance of the scheduler has been elevated, as it is the component that determines which applications utilize the resources each time period.In this thesis, we address cross-core interference on CMP platforms, by designing scheduling policies that improve performance and fairness. We deal with contention in three ways. In our first approach, we incorporate the notion of progress in order to balance unfairness among the applications of the workload. Performance degradation is not evenly distributed and progress greatly varies among them. In order to provide a fair execution environment, we monitor, at run-time, applications assigned to the CPU and prioritize them based on the extent at which they are affected by contention.In our second approach, we target performance by mitigating contention on shared resources. It is necessary to decide, out of all the possible application schedules, the one that generates the least amount of resource interference. To achieve that, the first indispensable step is to extract an interference profile for the applications executed on the CMP. We accomplish that by applying pressure to all levels of memory hierarchy and identifying the point at which performance is compromised. From our analysis, we understand that shared resources can tolerate pressure of certain amount; applications can be grouped together if the overall generated pressure does not reach the saturation point of the shared resources. Having extracted this information, we proceed to the placement of the application in such a way that overall resource requirements are as balanced as possible across the execution.Finally, we design a policy in order to improve performance and fairness at the same time. Applications that heavily rely on the LLC are separated from those with high main memory bandwidth, in order to avoid the destructive effects caused by the LLC thrashing behavior of the latter. The group executed on the CPU is determined based on the key observation that the overall requirements of the group should not exceed the saturation limits of the CMP. Additionally, during execution, the progress for each application is estimated and those with the least accumulated progress are prioritized.Our proposed policies are evaluated in an Intel Xeon E5-2620 v3 processor. A variety of benchmark suites were utilized to generate mixes of diverse characteristics. Our methodologies are implemented in user-space and can be deployed on Linux-based systems. Experimental results show the benefits of tackling contention in shared resources. We achieve throughput gains of up to 16% and unfairness is reduced by 2.37x on average compared to Linux scheduler.

Lab-on-a-chip devices are changing the way that medical testing is performed by allowing rapid testing with small samples. Optofluidic biosensors are a type of lab-on-a-chip device that use light excitation on a fluid sample. One such application of an optofluidic biosensor is a device that can detect antibiotic resistant bacteria by combining DNA from a sample with fluorescent beads, flowing that sample through a hollow channel, and shining laser light on the channel. If the bacteria tested for is present, the fluorescent beads will give off photons that can be detected as a positive signal. The main method for illumination for these devices has been coupling light through a fiber optic cable to a waveguide on the side of the chip. Though effective, this method is impractical in a real world setting such as a hospital due to the difficulty of aligning to the side of the device. One solution to this problem is the use of illumination from the top of the device. Top-down illumination allows for more alignment flexibility, but also introduces the risk of additional noise or false signal as extra light reflects of the device. This dissertation discusses the viability and development of top-down illumination for optofluidic biosensors. This includes the development of an anti-reflective layer compatible with optofluidic biosensors, comparison of top-down illumination to side illumination, and simulations of various methods of performing top-down illumination. Based on the research and findings discussed in this dissertation, it has been found that top-down illumination is a viable illumination method for optofluidic biosensors. Additionally, the use of a pattern of laser lines combined with a light blocking anti-reflective layer is the recommended method for top-down illumination.

A current trend in the semiconductor industry is the use of Multi-Processor Systems-on-Chip (MPSoCs) for a wide variety of applications such as image processing, automotive, multimedia, and robotic systems. Most applications gain performance advantages by executing parallel tasks on multiple processors due to the inherent parallelism. Moreover, heterogeneous structures provide high performance/energy efficiency, since application-specific processing elements (PEs) can be exploited. The increasing number of heterogeneous PEs leads to challenging communication requirements. To overcome this challenge, Networks-on-Chip (NoCs) have emerged as scalable on-chip interconnect. Nevertheless, NoCs have to deal with many design parameters such as virtual channels, routing algorithms and buffering techniques to fulfill the system requirements. This thesis highly contributes to the state-of-the-art of FPGA-based MPSoCs and NoCs. In the following, the three major contributions are introduced. As a first major contribution, a novel router concept is presented that efficiently utilizes communication times by performing sequences of arithmetic operations on the data that is transferred. The internal input buffers of the routers are exchanged with processing units that are capable of executing operations. Two different architectures of such processing units are presented. The first architecture provides multiply and accumulate operations which are often used in signal processing applications. The second architecture introduced as Application-Specific Instruction Set Routers (ASIRs) contains a processing unit capable of executing any operation and hence, it is not limited to multiply and accumulate operations. An internal processing core located in ASIRs can be developed in C/C++ using high-level synthesis. The second major contribution comprises application and performance explorations of the novel router concept. Models that approximate the achievable speedup and the end-to-end latency of ASIRs are derived and discussed to show the benefits in terms of performance. Furthermore, two applications using an ASIR-based MPSoC are implemented and evaluated on a Xilinx Zynq SoC. The first application is an image processing algorithm consisting of a Sobel filter, an RGB-to-Grayscale conversion, and a threshold operation. The second application is a system that helps visually impaired people by navigating them through unknown indoor environments. A Light Detection and Ranging (LIDAR) sensor scans the environment, while Inertial Measurement Units (IMUs) measure the orientation of the user to generate an audio signal that makes the distance as well as the orientation of obstacles audible. This application consists of multiple parallel tasks that are mapped to an ASIR-based MPSoC. Both applications show the performance advantages of ASIRs compared to a conventional NoC-based MPSoC. Furthermore, dynamic partial reconfiguration in terms of relocation and security aspects are investigated. The third major contribution refers to development and programming methodologies of NoC-based MPSoCs. A software-defined approach is presented that combines the design and programming of heterogeneous MPSoCs. In addition, a Kahn-Process-Network (KPN) –based model is designed to describe parallel applications for MPSoCs using ASIRs. The KPN-based model is extended to support not only the mapping of tasks to NoC-based MPSoCs but also the mapping to ASIR-based MPSoCs. A static mapping methodology is presented that assigns tasks to ASIRs and processors for a given KPN-model. The impact of external hardware components such as sensors, actuators and accelerators connected to the processors is also discussed which makes the approach of high interest for embedded systems.

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