La compréhension des mécanismes qui contrôlent l'expression des gènes est un enjeu majeur pour la recherche médicale. Elle nécessite un ensemble d'approches pangénomiques telles que les puces à ADN et plus récemment le séquençage à très haut débit qui génèrent une masse toujours plus grande de données numériques à traiter. Au cours de ma thèse, j'ai développé plusieurs outils informatiques innovants pour faciliter leur exploitation. Ainsi, j'ai créé une librairie R (AgiND) qui vérifie la qualité des données de puces à ADN Agilent et permet de les normaliser. Le nombre croissant d'expériences stockées dans Gene Expression Omnibus a motivé la mise en place du projet TBrowser. Une méthode originale DBF-MCL a été créée pour extraire des signatures transcriptionnelles annotées par l'intégration de diverses sources d'information. Stockées dans une base de données, elles sont accessibles à travers une interface Java, un service web SOAP et une librairie R/Bioconductor (RTools4TB). Enfin, un pipeline d'analyse dédié au ChIP-seq a été implémenté. Tous ces outils ont servi pour l'étude de diverses maladies dans le cadre de collaborations. / Understanding the mechanisms that control gene expression is a major challenge for medical research. This requires using a large set of pangenomic approaches such as those using DNA microarrays and high-throughput sequencing that generate an ever growing mass of digital data. During my thesis, I have developed several computer-based tools to facilitate their processing and analysis. I have created a R library (AgiND) that controls the quality of Agilent DNA microarray data and allows their statistical normalization. The growing number of experiences stored in Gene Expression Omnibus has motivated the development of the TBrowser project. An original method, DBF-MCL, was created to extract annotated transcriptional signatures by integrating various sources of information. Stored in a database, these signatures are accessible using a Java interface, a SOAP web service and a R/Bioconductor library (RTools4TB). Finally, a pipeline dedicated to the ChIP-seq analyses has been implemented. All these tools were used to study various diseases in collaborations.

<p>This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.</p>

<p>The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performancewhile the delay of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. In fact, global interconnects extending across a full chip can have a delay corresponding to multiple clock cycles. At the same time, global clock skew constraints, not only between blocks but also along the pipelined interconnects, become even tighter. On-chip interconnects have always been considered <em>RC</em>-like, that is exhibiting long <em>RC</em>-delays. This has motivated large efforts on alternatives such as on-chip optical interconnects, which have not yet been demonstrated, or complex schemes utilizing on-chip F-transmission or pulsed current-mode signaling.</p><p>In this thesis, we show that well-designed electrical global interconnects, behaving as transmission lines, have the capacity of very high data rates (higher than can be delivered by the actual process) and support near velocity-of-light delay for single-ended voltage-mode signaling, thus mitigating the <em>RC</em>-problem. We critically explore key interconnect performance measures such as data delay, maximum data rate, crosstalk, edge rates and power dissipation. To experimentally demonstrate the feasibility and superior properties of on-chip transmission line interconnects, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over the 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 μm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum.</p><p>To manage the problems due to global wire delays, we describe and implement a Synchronous Latency Insensitive Design (SLID) scheme, based on source-synchronous data transfer between blocks and data re-timing at the receiving block. The SLIDtechnique not onlymitigates unknown globalwire delays, but also removes the need for controlling global clock skew. The high-performance and high robustness capability of the SLID-method is practically demonstrated through a successful implementation of a SLID-based, 5.4 mm long, on-chip global bus, supporting 3 Gb/s/wire and dynamically accepting ± 2 clock cycles of data-clock skew, in a standard 0.18 μm CMOS porcess.</p><p>In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition-energy cost model aimed for efficient power estimation of performancecritical buses. The model, which includes properties that closely capture effects present in high-performance VLSI buses, can be used to more accurately determine the energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a microprocessor cache bus architecture used in industry.</p>

Thesis (Ph. D.)--Princeton University, 2005. / "June 2005." Description based on contents viewed Apr. 11, 2007; title from title screen. Includes bibliographical references (p. 135-147).

In der molekularen Diagnostik besteht ein Bedarf an schnellen und spezifischen Testsystemen, die entweder für die Labordiagnostik oder in Point of Care-Umgebungen eingesetzt werden können. Um dieses Ziel zu erreichen, stehen die Miniaturisierung und Parallelisierung im Mittelpunkt des Forschungsinteresses. Die führende Methode im Bereich der DNA-Analytik ist derzeit die Realtime-PCR. Dieser Technologie sind hinsichtlich der Multiplexfähigkeit technologischen Hürden gesetzt, da derzeit nur eine Analyse von maximal vier Parametern parallel in einem Versuchsansatz erfolgen kann. Microarrays stellen hingegen die benötigten Voraussetzungen zur Verfügung, um als Werkzeuge für die Multiparameteranalyse in verschiedensten Anwendungsbereichen zu dienen. Ein Schwerpunkt dieser Arbeit war es, Multiplex-PCRs und diagnostische Microarrays zu entwickeln, die für analytische Fragestellungen eine schnelle und zuverlässige Multiparameteranalytik ermöglichen, um die bisherigen Einschränkungen aktueller Nachweisverfahren zu vermeiden. Als Anwendungen wurden zum einen ein Nachweissystem für acht relevante Geflügelpathogene zur Überwachung in der Geflügelzucht, zum anderen ein Nachweissystem zur Identifikation potentiell allergener Lebensmittelinhaltstoffe entwickelt. Neben der Entwicklung geeigneter PCR und Multiplex-PCR-Verfahren sowie spezifischer Microarrays für die Detektion der gesuchten Zielsequenzen stand auch die weiterführende Integration von DNA-Amplifikation und Microarray-Technologie im Fokus dieser Arbeit. Die OnChip-Amplifikation stellt eine Möglichkeit dar, um DNA-Analytik und Detektion in einem Reaktionsschritt zu integrieren. Entsprechend wurden die in der Arbeit entwickelten PCR- und Multiplex-PCR-Verfahren zum Nachweis potentieller allergener Lebensmittelinhaltsstoffe für die OnChip-Amplifikation adaptiert und Reaktionsbedingungen getestet, die eine Multiparameteranalyse auf dem Chip ermöglichen. Die entwickelten OnChip-PCR-Verfahren zeigten eine hohe Spezifität sowohl in Single- als auch in der Multiplex-OnChip-PCR. Eine Sensitivität von 10 Kopien bzw. <10ppm konnte in Single-OnChip-PCRs für den Nachweis allergener Lebensmittelinhaltsstoffe gezeigt werden. In Multiplex-OnChip-PCRs konnten 10-100ppm allergene Verunreinigungen spezifisch in unterschiedlichen Lebensmitteln nachgewiesen werden. Ein weiterer Schritt in Richtung einer möglichen Verwendung im Point of Care-Bereich stellt der Einsatz eines isothermalen Amplifikationsverfahrens dar. Vorteil eines solchen Verfahrens ist die Möglichkeit, auf das ansonsten benötigte Thermocycling zu verzichten. Dies vereinfacht eine Integration der OnChip-Amplifikation in mobile Analysegeräte oder Lab on Chip-Systeme und qualifiziert das Verfahren für den Einsatz in Point of Care-Umgebungen. In dieser Arbeit wurde eine noch junge isothermale Amplifikationsmethode, die helikase-abhängige Amplifikation (HDA), hinsichtlich ihrer Eignung für die Integration auf einem Microarray getestet. Hierfür konnte die bislang erste OnChip-HDA für Einzel- und Duplex-Nachweise von Pathogenen entwickelt werden. / In molecular diagnostics there is a need for fast and specific assay systems that could be used in the clinics and in point of care settings alike. Therefore miniaturisation and parallelisation are in the main focus of current assay development researches. The current gold standard for DNA analytics is the realtime PCR. However, this technology has its restraints in context to multiplex analysis. With the currently available technology an efficient multiplexing is only possible for four different targets per analysed sample. Microarrays in contrast offer the needed multiplex capabilities and have advanced to capable tools used in multiple fields of application. One focus of this work was the integration of Multiplex PCR and microarray technology, developing a microarray capable of analysing multiple parameters in one given sample, circumventing the problems and restraints of the exsisting technologies. As an example microarray assays for two different application fields were developed. One microarray assay for the detection of pathogens in poultry and another microarray assay for the detection of potentially allergenic food ingredients. Single- and Multiplex OnChip-PCR assays for both applications were developed and tested. OnChip-PCRs developed in this work showed high specificity in Single- and Multiplex-OnChip amplifications. The sensitivity was in the range of 10 DNA copies or 10ppm respectively for Single-OnChip-PCR in experiments for the detection of allergenic food contaminations. In Multiplex-OnChip-PCR experiments 100 DNA copies or 100ppm of food contaminents could be detected in different food matrices. A further focus of this work was the adaption of the OnChip amplification for the use in Point of Care settings. Isothermal amplification is a promising approach having the advantage of avoiding the thermocycling needed in the PCR. This opens up certain opportunities for the development of smaller, more flexible mobile diagnostic analysis devices. In this work we have evaluated the helicase dependent amplification (HDA) in terms of usability in OnChip amplification. In this work it was shown for the first time that HDA could be used for the detection of different pathogens in an Duplex-OnChip-PCR, showing the potential of this technology for integration in Point of Care settings.

The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performancewhile the delay of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. In fact, global interconnects extending across a full chip can have a delay corresponding to multiple clock cycles. At the same time, global clock skew constraints, not only between blocks but also along the pipelined interconnects, become even tighter. On-chip interconnects have always been considered RC-like, that is exhibiting long RC-delays. This has motivated large efforts on alternatives such as on-chip optical interconnects, which have not yet been demonstrated, or complex schemes utilizing on-chip F-transmission or pulsed current-mode signaling. In this thesis, we show that well-designed electrical global interconnects, behaving as transmission lines, have the capacity of very high data rates (higher than can be delivered by the actual process) and support near velocity-of-light delay for single-ended voltage-mode signaling, thus mitigating the RC-problem. We critically explore key interconnect performance measures such as data delay, maximum data rate, crosstalk, edge rates and power dissipation. To experimentally demonstrate the feasibility and superior properties of on-chip transmission line interconnects, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over the 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 μm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum. To manage the problems due to global wire delays, we describe and implement a Synchronous Latency Insensitive Design (SLID) scheme, based on source-synchronous data transfer between blocks and data re-timing at the receiving block. The SLIDtechnique not onlymitigates unknown globalwire delays, but also removes the need for controlling global clock skew. The high-performance and high robustness capability of the SLID-method is practically demonstrated through a successful implementation of a SLID-based, 5.4 mm long, on-chip global bus, supporting 3 Gb/s/wire and dynamically accepting ± 2 clock cycles of data-clock skew, in a standard 0.18 μm CMOS porcess. In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition-energy cost model aimed for efficient power estimation of performancecritical buses. The model, which includes properties that closely capture effects present in high-performance VLSI buses, can be used to more accurately determine the energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a microprocessor cache bus architecture used in industry.

QC 20101018

This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.

Environmental stress tests, or accelerated life tests, apply stresses to electronic packages that exceed the stress levels experienced in the field. In theory, these elevated stress levels are used to generate the same failure mechanisms that are seen in the field, only at an accelerated rate. The methods of assessing reliability of electronic packages can be classified into two categories: a statistical failure based approach and a physics of failure based approach. This research uses a statistical based methodology to identify the critical factors in reliability performance of a flip chip on board component level assembly and a physics of failure based approach to develop a low cycle strain based fatigue equation for flip chip component level assemblies. The critical factors in determining reliability performance were established via experimental investigation and their influence quantified via regression analysis. This methodology differs from other strain based fatigue approaches because it is not an empirical fit to experimental data; it utilizes regression analysis and least squares to obtain correction factors, or correction functions, and constants for a strain based fatigue equation, where the total inelastic strain is determined analytically. The end product is a general flip chip on board equation rather than one that is specific to a certain test vehicle or material set.

No description available.