Ao longo dos últimos anos, os sistemas embarcados vêm se tornando cada vez mais complexos tanto em termos de hardware quanto de software. Ultimamente têm-se adotado como solução o uso de MPSoCs (sistemas multiprocessados integrados em chip) para uma maior eficiência energética e computacional nestes sistemas. Com o uso de diversos elementos de processamento, redes-em-chip (NoC - networks-on-chip) aparecem como soluções de melhor desempenho do que barramentos. Nestes ambientes cujo desempenho depende da eficiência do modelo de comunicação, a hierarquia de memória se torna um elemento chave. Baseando-se neste cenário, este trabalho realiza uma investigação sobre o impacto da hierarquia de memória em MPSoCs baseados em NoC. Dentro deste escopo foi desenvolvida uma nova organização de memória fisicamente centralizada com diferentes espaços de endereçamentos denominada nDMA. Este trabalho também apresenta uma comparação entre a nova organização e outras três organizações bastante difundidas tais como memória distribuída, memória compartilhada e memória compartilhada distribuída. Estas duas ultimas adotam um modelo de coerência de cache baseado em diretório completamente desenvolvido em hardware. Os modelos de memória foram implementados na plataforma virtual SIMPLE (SIMPLE Multiprocessor Platform Environment). Resultados experimentais mostram uma forte dependência com relação à carga de comunicação gerada pelas aplicações. O modelo de memória distribuída apresenta melhores resultados conforme a carga de comunicação das aplicações é baixa. Por outro lado, o novo modelo de memória fisicamente compartilhado com diferentes espaços de endereçamento apresenta melhores resultados conforme a carga de comunicação das aplicações é alta. Também foram realizados experimentos objetivando analisar o desempenho dos modelos de memória em situações de alta latência de comunicação na rede. Resultados mostram melhores resultados do modelo de memória distribuída quando a carga de comunicação das aplicações é alta e, caso contrário, o modelo nDMA apresenta melhores resultados. Por fim, foram analisados os desempenhos dos modelos de memória durante o processo de migração de tarefas. Neste caso, os modelos de memória compartilhada e compartilhada distribuída apresentaram melhores resultados devido ao fato de que não se faz necessária o envio dos dados da aplicação nestes modelos e também devido ao menor tamanho de código se comparado com os outros modelos. / In the past few the years, embedded systems have become even more complex both on terms of hardware and software. Lately, the use of MPSoCs (Multi-Processor Systems-on-Chip) has been adopted on these systems for a better energetic and computational efficiency. Due to the use of several processing elements, Networks-on-Chip arise as better performance solutions than buses. Considering this scenario, this work performs an investigation on the impact of memory hierarchy in NoC-based MPSoCs. In this context, a new physically centralized and shared memory organization with different address spaces named nDMA was developed. This work also presents a comparison between the new memory organization and three different well-known memory hierarchy models such as distributed memory and shared and distributed shared memories that make use of a fully hardware cache coherence solution. The memory models were implemented in the SIMPLE (SIMPLE Multiprocessor Platform Environment) virtual platform. Experimental results shows a strong dependency on the application communication workload. The distributed memory model presents better results as the application communication workload is low. On the other hand, the new memory model (physically shared with different address spaces) presents better results as the application communication workload is high. There were also experiments aiming at observing the performance of the memory models in situations where the communication latency on the network is high. Results show better results of the distributed memory model when the application communication workload is high, and the nDMA model presents better results otherwise. Finally, the performance of the memory models during a task migration process were evaluated. In this case, the shared memory and distributed shared memory models presented better results due to the fact that in this case the data memory does not need to be transferred from one point to another and also due to the low size of the memory code in these cases if compared to other memory models.

Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas com múltiplos processadores num chip (MPSoCs, do inglês MultiProcessor System-on-Chip). Essa possibilidade de integração permite inserir dezenas de Elementos de Processamento (EPs) nos circuitos integrados atuais, e já se projeta centenas de EPs para os sistemas da próxima década (ITRS, 2011). Nesse cenário, um dos principais desafios se refere ao serviço de interconexão dos EPs, que deve apresentar um desempenho de comunicação necessário para as aplicações em execução sem comprometer as limitações de consumo de área e energia do circuito. Nos primeiros sistemas multiprocessados, com poucos nodos, arquiteturas baseadas em barramento foram suficientes para cumprir esses requisitos. Porém, o número de elementos nos sistemas recentes aumentou rapidamente, tornando as redes-em-chip a solução mais apropriada, por aliar escalabilidade e reuso na mesma estrutura. Contudo, diante da previsão de que essa tendência de aumento se manterá retorna a discussão se as redes-em-chip atuais continuarão adequadas para os futuros sistemas. De fato, o custo das redes-em-chip convencionais pode se tornar proibitivo para as escalas dos circuitos em um futuro próximo. Novas propostas têm sido apresentadas na literatura científica onde se podem destacar duas principais estratégias de projeto às redes de interconexão: reconfiguração arquitetural e organização hierárquica da topologia. A reconfiguração arquitetural permite obter uma grande eficiência, independente do tipo de aplicação em execução, pois uma das alternativas é projetar o circuito para que ele se auto adapte conforme os requisitos de desempenho para cada aplicação. Por outro lado, arquiteturas organizadas em topologias hierárquicas são desenvolvidas para uma estrutura computacional definida em tempo de projeto, sendo mais eficazes para uma classe de aplicações. O presente trabalho explora a sinergia da combinação das potencialidades das duas soluções e propõe uma nova estrutura que oferece melhor desempenho para uma classe maior de aplicações apropriada para os futuros sistemas. Como resultado foi implementada uma arquitetura adaptativa chamada MINoC (Multiple Interconnections Networks-on-Chip), uma arquitetura organizada em hierarquia, chamada HiCIT (Hierarchical Crossbar-based Interconnection Topology) e uma simbiose de ambas culminando na arquitetura hierárquica adaptativa HASIN (Hierarchical Adaptive Switching Interconnection Network). São apresentados resultados que mostram a eficiência desses conceitos validando a proposta hierárquica adaptativa. / With the advent of submicron processes, the number of transistors integrated on a single chip has reached levels that allowed the design of Multiprocessor Systems-on-Chip (MPSoCs). This capability allows the integration of several processing elements (PEs) in integrated circuits designed nowadays. In the next decade it is expected that hundreds of PEs will be integrated on a single chip. In this scenario, a key challenge is the interconnection network between PEs, which must provide the communication service required to run applications without compromising the limitations of area and energy consumption. In the first multiprocessor systems, with few nodes, bus-based approaches have been sufficient to meet these requirements. However, current systems increased quickly the number of elements, making the Networks-on-Chip (NoCs) the most appropriate solution, because it handles scalability and reusability in the same structure. Nevertheless, ITRS roadmap predicts that this increase will continue (ITRS, 2011), which resumes the discussion if present NoC architectures will be the most adequate for future systems, since its costs could be prohibitive. Therefore, new proposals have been presented in the literature with two main design strategies: architectural reconfiguration and hierarchical organization of the topology. With the architectural reconfiguration it is possible to obtain an application independent high efficiency structure, because the circuit is designed to adapt itself to satisfy performance requirements. On the other hand, architectural organizations in hierarchical topologies are defined at design time to have the most appropriate features for a class of applications, being very effective. The current work identified the synergy of both approaches and proposes a new symbiotic structure suitable for a broader class of applications. As a result, it was implemented an adaptive architecture called MINoC (Multiple Interconexions Networks-on-chip), an architecture organized in hierarchy called HiCIT (Hierarchical Crossbar-based Interconnection Topology) and a mix of both ending up with the hierarchical adaptive architecture HASIN (Hierarchical Interconnection Network Adaptive Switching). Results show the efficiency of these concepts validating the proposed hierarchical adaptive architecture.

A complexidade no projeto de sistemas eletrônicos tem aumentado devido à evolução tecnológica e permite a concepção de sistemas inteiros em um único chip (SoCs – do inglês, Systems-on-Chip). Com o objetivo de reduzir a alta complexidade de projeto, custos de projeto e o tempo de lançamento do produto no mercado, os sistemas são desenvolvidos em módulos funcionais, pré-verificados e pré-projetados, denominados de núcleos de propriedade intelectual (IP – do inglês, Intellectual Property). Esses núcleos IP podem ser reutilizados de outros projetos ou adquiridos de terceiros. Entretanto, é necessário prover uma estrutura de comunicação para interligar esses núcleos e as estruturas atuais (barramentos) são inadequadas para atender as necessidades dos futuros SoCs (compartilhamento de banda, falta de escalabilidade). As redes-em-chip (NoCs{ XE "NoCs" } – do inglês, Networks-on-Chip) vêm sendo apresentadas como uma solução para atender essas restrições. No desenvolvimento de sistemas embarcados baseados em redes-em-chip, deve-se personalizar a rede para atendimento de restrições. Essa exploração de espaço de projeto (EEP), segundo uma infinidade de trabalhos, é realizada em tempo de projeto, supondo-se que é conhecido o perfil das aplicações que devem ser executadas pelo sistema. No entanto, cada vez mais sistemas embarcados aproximam-se de dispositivos genéricos de processamento (como palmtops), onde as tarefas a serem executadas não são inteiramente conhecidas a priori. Com a mudança dinâmica da carga de trabalho de um sistema embarcado, a busca pelo atendimento de requisitos pode então ser enfrentada por mecanismos adaptativos, que implementam dinamicamente a EEP. No âmbito deste trabalho, a EEP em tempo de execução provê mecanismos adaptativos que deverão realizar suas funções para atendimento de restrições de projeto. Consequentemente, EEP em tempo de execução pode permitir resultados ainda melhores, no que diz respeito a sistemas embarcados com restrições de projetos rígidas. É possível maximizar o tempo de duração da energia da bateria que alimenta um sistema embarcado ou, até mesmo, diminuir a taxa de perda de deadlines em um sistema de tempo real soft, realocando em tempo de execução tarefas de modo a gerar menor taxa de comunicação entre os processadores, desde que o sistema seja executado em um tempo suficiente para amortizar os custos de migração. Neste trabalho, foi utilizada a combinação de heurísticas de alocação da área dos Sistemas Computacionais Distribuídos como, por exemplo, algoritmos bin-packing e linear clustering. Resultados mostraram que a realocação de tarefas, utilizando uma combinação Worst-Fit e Linear Clustering, reduziu o consumo de energia e a taxa de perda de deadlines em 17% e 37%, respectivamente, utilizando o modelo de migração por cópia. / The complexity of electronic systems design has been increasing due to the technological evolution, which now allows the inclusion of a complete system on a single chip (SoC – System-on-Chip). In order to cope with the corresponding design complexity and reduce design costs and time-to-market, systems are built by assembling pre-designed and pre-verificated functional modules, called IP (Intellectual Property) cores. IP cores can be reused from previous designs or acquired from third-party vendors. However, an adequate communication architecture is required to interconnect these IP cores. Current communication architectures (busses) are unsuitable for the communication requirements of future SoCs (sharing of bandwidth, lack of scalability). Networks-on-Chip (NoC) arise as one of the solutions to fulfill these requirements. While developing NoC-based embedded systems, the NoC customization is mandatory to fulfill design constraints. This design space exploration (DSE), according to most approaches in the literature, is achieved at compile-time (off-line DSE), assuming the profiles of the tasks that will be executed in the embedded system are known a priori. However, nowadays, embedded systems are becoming more and more similar to generic processing devices (such as palmtops), where the tasks to be executed are not completely known a priori. Due to the dynamic modification of the workload of the embedded system, the fulfillment of requirements can be accomplished by using adaptive mechanisms that implement dynamically the DSE (run-time DSE or on-line DSE). In the scope of this work, DSE is on-line. In other words, when the system is running, adaptive mechanisms will be executed to fulfill the requirements of the system. Consequently, on-line DSE can achieve better results than off-line DSE alone, especially considering embedded systems with tight constraints. It is thus possible to maximize the lifetime of the battery that feeds an embedded system, or even to decrease the deadline miss ratio in a soft real-time system, for example by relocating tasks dynamically in order to generate less communication among the processors, provided that the system runs for enough execution time in order to amortize the migration overhead.In this work, a combination of allocation heuristics from the domain of Distributed Computing Systems is applied, for instance bin-packing and linear clustering algorithms. Results shows that applying task reallocation using the Worst-Fit and Linear Clustering combination reduces the energy consumption and deadline miss ratio by 17% and 37%, respectively, using the copy task migration model.

Submitted by Fabio Sobreira Campos da Costa (fabio.sobreira@ufpe.br) on 2016-03-15T13:58:26Z No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) UFPE-MEI 2015-078 - Maria Cireno Ribeiro Silveira.pdf: 4578273 bytes, checksum: 1c434494e0c03cb02156a37ebfd1c7da (MD5) / Made available in DSpace on 2016-03-15T13:58:26Z (GMT). No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) UFPE-MEI 2015-078 - Maria Cireno Ribeiro Silveira.pdf: 4578273 bytes, checksum: 1c434494e0c03cb02156a37ebfd1c7da (MD5) Previous issue date: 2015-03-09 / O prefetching é uma técnica considerada e ciente para mitigar um problema já conhecido em sistemas computacionais: a diferença entre o desempenho do processador e do acesso à memória. O objetivo do prefetching é aproximar o dado do processador retirando-o da memória e carregando na cache local. Uma vez que o dado seja requisitado pelo processador, ele já estará disponível na cache, reduzindo a taxa de perdas e a penalidade do sistema. Para sistemas multiprocessadores baseados em NoCs a e ciência do prefetching é ainda mais crítica em relação ao desempenho, uma vez que o tempo de acesso ao dado varia dependendo da distância entre processador e memória e do tráfego da rede. Este trabalho propõe um algoritmo de prefetching de dados temporizado, que tem como objetivo minimizar a penalidade dos núcleos através uma solução de prefetching baseada em predição de tempo para sistemas multiprocessadores baseados em NoC. O algoritmo utiliza um processo pró-ativo iniciado pelo servidor para realizar requisições de prefetching baseado no histórico de perdas de cache e informações da NoC. Nos experimentos realizados para 16 núcleos, o algoritmo proposto reduziu a penalidade dos processadores em 53,6% em comparação com o prefetching baseado em eventos (faltas na cache), sendo a maior redução de 29% da penalidade. / The prefetching technique is an e ective approach to mitigate a well-known problem in multi-core processors: the gap between computing and data access performance. The goal of prefetching is to approximate data to the CPU by retrieving the data from the memory and loading it in the cache. When the data is requested by the CPU, it is already available in the cache, reducing the miss rate and penalty. In multiprocessor NoC-based systems the prefetching e ciency is even more critical to system performance, since the access time depends of the distance between the requesting processor and the memory and also of the network tra c. This work proposes a temporized data prefetching algorithm that aims to minimize the penalty of the cores through one prefetching solution based on time prediction for multiprocessor NoC-based systems. The algorithm utilizes a proactive process initiated by the server to request prefetching data based on cache miss history and NoC's information. In the experiments for 16 cores, the proposed algorithm has successfully reduced the processors penalty in 53,6% compared to the event-based prefetching and the best case was a penalty reduction of 29%.

Submitted by Fabio Sobreira Campos da Costa (fabio.sobreira@ufpe.br) on 2016-07-01T13:03:48Z No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) dissertacao_Camila_Ascendina_Nunes_Kamei.pdf: 2427056 bytes, checksum: 9c4bd5bb499271557f86edce757edec2 (MD5) / Made available in DSpace on 2016-07-01T13:03:48Z (GMT). No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) dissertacao_Camila_Ascendina_Nunes_Kamei.pdf: 2427056 bytes, checksum: 9c4bd5bb499271557f86edce757edec2 (MD5) Previous issue date: 2015-08-07 / CNPq / Duas questões são críticas em sistemas com paralelismo de memória em rede NoC baseados em MPSoC, a ordem de entrega da mensagem e o congestionamento da rede. Os congestionamentos são frequentes em NoC quando as demandas de pacotes excedem a capacidade dos recursos da rede e a ordem das mensagens precisam ser mantidas para que a informação de coerência de cache tenha signi cado para as memórias. Assim, métodos de controle de congestionamento são necessários para estes sistemas e devem lidar com o congestionamento da rede, enquanto mantém a ordem das transações. Este trabalho propõe uma técnica de roteamento baseada no algoritmo de roteamento Odd-Even associado ao conceito de congestionamento local e global da rede para a escolha do melhor caminho de encaminhamento dos pacotes de comunicação. Desta forma se objetiva a redução dos gargalos de comunicação da rede para os sistemas NoC baseado em MPSoC. Nos experimentos realizados para 16 núcleos, a técnica proposta alcançou a redução de 13,35% da energia consumida, 25% de redução de latência de envio de pacotes em comparação o algoritmo XY e 23% de redução de latência de envio de pacotes em comparação o algoritmo Odd-Even sem modi cação. / Two issues are critical in systems with memory parallelism network NoC-based MPSoC, the delivery order of messages and network congestion. The congestions are frequent in NoC when the packages demands exceed the capacity of the network resources and the order of the messages need to be maintained so that the cache coherency information is meaningful to the memories. Thus, congestion control methods are needed to deal with network congestion while they keep the order of the transactions. This paper proposes the use of the routing algorithm Odd-Even associated with the concept of local and global network congestion to choose the best routing path of communication packages. In this way it aims to reduce the network communication bottlenecks for NoC systems based on MPSoC. In experiments conducted for 16 cores, the proposed technique has achieved the reduction of 13.35 % of energy consumption, 25% of latency compared with the XY algorithm and 23% of latency compared with the Odd-Even algorithm without the modi cation.

Este trabalho descreve o desenvolvimento de um processo de fabricação de mini e microdispositivos fluídicos baseado na utilização de um equipamento de usinagem a laser de CO2 para criação de relevos sobre base de poli(metacrilato de metila) e na selagem térmica contra igual material. Inicialmente, o equipamento laser foi detalhadamente caracterizado, o que possibilitou elaborar métodos para a construção de microcanais de forma mais eficiente e com menores chances de defeitos. Tipicamente, os canais apresentaram seção transversal triangular em torno de 200 µm de largura e 100 µm de profundidade, sendo possível, no entanto, criar canais com outras características. A etapa de selagem entre a tampa e a base que apresentou melhores resultados consiste em pressurização acima de 6 kgf·cm-2 e aquecimento a 110 ºC durante 45 minutos, seguido de resfriamento por 1 h. Os microcanais selados por esta técnica, resistiram a pressões superiores a 3,5·kgf·cm-2. O processo desenvolvido se mostrou adequado para a criação de protótipos, sendo também suas principais características: (1) a facilidade de incorporação de regiões de grandes dimensões (como reservatórios) em conjunto com os microcanais, (2) número reduzido de etapas de produção e (3) boa uniformidade química da parede interna dos canais, o que é particularmente interessante para microdispositivos aplicados à Química Analítica / A microfabrication process based machining using CO2 laser on poly(methyl methacrylate) and thermal sealing is described. Initially, the laser equipment was characterized in detail, which allowed developing strategies for the construction of microchannels more efficiently and less failure-prone. Typically, the channels had a triangular cross section around 200 µm in width and 100 µm in depth. It is possible, however, create channels with other features. The sealing step that showed better results consists in to pressurize at 6 kgf·cm-2 and heating at 110 °C during 45 minutes, followed by natural cooling for 1 h. The microchannels sealed by using this procedure resisted pressures above 3.5 kgf·cm-2. The process proved to be adequate for prototyping and also has other main features: (1) easiness of incorporation of large regions (such as reservoirs) together with the microchannel; (2) reduced number of manufacturing steps and (3) good chemical uniformity of the inner wall of the channel, which is particularly interesting for microdevices applied to Analytical Chemistry.

Atualmente, o Brasil é considerado o maior exportador mundial e terceiro maior produtor mundial de carne de frango. Este destaque é resultado, principalmente, do melhoramento animal baseado na estimação do valor genético a partir da mensuração de fenótipos e informações de pedigree. Entretanto, é comum que a seleção não seja feita para cada característica isoladamente devido à correlação genética entre elas. Esta correlação tem como causas a pleiotropia ou a ligação genética. Com este trabalho objetivou-se detectar associações entre características fenotípicas de interesse para a avicultura e SNPs em uma região do cromossomo 1 (168 - 208 cM e 57 - 71 Mbp), onde possíveis QTL ligados foram previamente mapeados. Utilizou-se o Beadchip de SNPs de 60k para genotipar 14 animais da geração Parental (machos TT e fêmeas CC) e 28 F1 da população TCTC desenvolvida pela Embrapa Suínos e Aves. A linhagem TT apresentou maior variabilidade genotípica que CC, porém, os F1 foram superiores às linhagens Parentais com base no número de heterozigotos e MAF. O polimorfismo com maior ocorrência em ambas as gerações foram as transições com 84,3%. Foram selecionados 144 SNPs mais informativos com base na heterozigosidade dos cinco casais F1 que geraram os 453 F2. Houve redução de heterozigotos e MAF em F2, em função da média de F1, decorrente de certo grau de parentesco e endogamia entre os animais que compuseram esta geração. Os blocos de haplótipos construídos demonstraram que os machos TT apresentaram 25 blocos, fêmeas CC (17), F1 (32) e F2 (23) com tamanho médio de 278, 467, 242 e 160 kpb, respectivamente. Foi evidenciado que 236 (42,7%) correlações fenotípicas foram significativas, das quais o maior número constatado foi entre PB_MS e outras 17 características e, o maior valor estimado foi entre PB_MS e EE_MS (-0,90). Do total esperado de 3.456 testes de associação, 609 (17,6%) foram considerados significativos (p < 0,05), sendo 424 (69,6%) com efeito aditivo e 185 com efeito de dominância (30,4%). PV41 apresentou maior número de associações (123), enquanto DOR não foi associado a nenhum SNP. Proporcionalmente, o maior número de SNPs foi associado próximo ao QTL pleiotrópico 2 para 17 características. Já os maiores níveis de significância (p < 9,59 x 10-8) para o efeito aditivo foram evidenciados para SNPs localizados próximos ao QTL pleiotrópico 1 e associados somente com PV41, a saber: Gga_rs13869715 (A < C), Gga_rs13870613 (T < C), Gga_rs14827719 (A < G), GGaluGA019336 (T < C) e GGaluGA019533 (A < C). Foram detectadas associações ainda não descritas na literatura para GP3541, CA3541, INT, PES, CAB, FIG, COR, MOE, PUL, HEM, COL, TRI, TC, PB_MS, EE_MS, CZ_MS. Finalmente, foram indicados possíveis genes candidatos posicionais e funcionais, tais como, IGF1, MYBPC1, MTPN, SOX-5, FGFR1OP2 e TTLL12 que poderão ser empregados na análise de expressão gênica. / Actually, Brazil is considered the world\'s first- and third-biggest exporter and producer of poultry meat, respectively. These performances are mainly consequence of animal breeding based on the estimation of breeding value combining phenotypes and pedigree information. However, usually the selection is not carried out for each trait separately due to genetic correlation between them. This correlation is caused by pleiotropy or linkage. We aimed to detect associations between phenotypic traits of interest to poultry industry and SNPs on a region of chromosome 1 (168 - 208 cM and 57 - 71 Mbp), where putative linked-QTL were previously mapped. A chicken 60k SNP BeadChip was used to genotype 14 animals from Parental generation (TT males and CC females) and 28 F1 of the TCTC population that was developed by Embrapa Swine and Poultry. The TT line showed greater genotypic variability than CC, however, F1 were higher than Parental generation based on the number of heterozygotes and MAF. The polymorphism more frequent in both generations was the transitions with 84.3%. The 144 most informative SNPs were selected based on heterozygosity of the five F1 couples which generated the 453 F2. There was a reduction of heterozygotes and MAF in F2, based on the F1 mean value, as consequence of some degree of relationship and inbreeding between animals that formed this generation. Haplotype blocks demonstrated that the TT males showed 25 blocks, CC female (17) F1 (32) and F2 (23) with an average size of 278, 467, 242 and 160 kbp, respectively. It was observed that 236 (42.7%) phenotypic correlations were significant. Out of these, the highest number was found between PB_MS and other 17 traits and the highest estimated value was between PB_MS and EE_MS (-0.90). Out of 3,456 expected association tests, 609 (17.6 %) were considered significant (p < 0.05), being 424 (69.6%) with additive effect and 185 with dominance effect (30.4%). PV41 presented the highest number of associations (123), while DOR was not associated to any SNP. Proportionally, the highest number of SNPs was associated close to the pleiotropic QTL 2 with 17 traits. On the other hand, the highest significance levels (p < 9.59 x 10-8) for the additive effect were evidenced for SNPs located close to the pleiotropic QTL 1 and associated only with PV41 (Gga_rs13869715 (A < C), Gga_rs13870613 (T < C), Gga_rs14827719 (A < G), GGaluGA019336 (T < C) and GGaluGA019533 (A < C)). Novel associations were detected for GP3541, CA3541, INT, PES, CAB, FIG, COR, MOE, PUL, HEM, COL, TRI, TC, PB_MS, EE_MS, CZ_MS when we compared our results with literature. Finally, putative positional and functional candidate genes were indicated such as IGF1, MYBPC1, MTPN, SOX-5, FGFR1OP2 and TTLL12, which may be used in gene expression analysis.

Les gliomes sont les tumeurs primitives les plus fréquentes du cerveau et restent de mauvais pronostic en raison de l’inefficacité des traitements actuels. Des cellules souches cancéreuses ont été isolées à partir de gliomes de haut grade de l’adulte. Ces cellules souches de gliomes (GSC) peuvent fournir tous les sous-types cellulaires qui composent la tumeur. De nombreuses données indiquent que la résistance aux traitements est due en grande partie aux GSC. Cibler les GSC et leurs propriétés souches constitue donc un enjeu thérapeutique important. [...] Une solution pertinente de ciblage thérapeutique est de forcer les GSC à quitter leur état souche. Dans ce cadre, mes principaux travaux ont eu pour but de caractériser les changements épigénétiques des marques d’histones qui accompagnent la répression des propriétés des GSC par un groupe de micro-ARN, miR-302-367. [...] L’étude de cette plasticité par notre équipe a abouti à l’identification de miR-302-367. Son expression forcée, à l’aide de lentivirus, bloque de façon irréversible les propriétés souches et initiatrices de tumeur des GSC. L’effet suppresseur de tumeur exercé par miR offre la possibilité d’identifier les mécanismes qui régulent le maintien ou la perte des propriétés des GSC. A l’aide d’un modèle formé par une lignée de GSC et de sa contrepartie dépourvue des propriétés souches et tumorigènes GSC-miR-302-367, je me suis attachée à caractériser les méthylations de l’histone H3, qui font parties du code d’histone associé à une transcription génique respectivement active ou réprimée. Je me suis axée sur la triméthylation de la lysine 4 (H3K4me3) et de la lysine 27 (H3K27me3), respectivement permissive et répressive de la transcription. Une analyse par ChIP-seq (Immunoprécipitation de la chromatine-séquençage) des gènes associés à ces marques a été associée à la caractérisation des transcriptomes des cellules par exon-array. Nos résultats montrent que l’expression du groupe de miR-302-367 ne modifie pas de façon globale les taux des marques H3K4me3 et H3K27me3. Par contre, des changements dans des groupes de gènes circonscrits ont pu être identifiés. La corrélation positive observée entre les marques d’histones et les taux d’expression des gènes montre une conservation du code d’histone dans les cellules cancéreuses, au moins pour les marques étudiées. L’analyse des termes GO (Gene Ontology) indique que la perte des propriétés induites par miR-302-367 s’accompagne d’un engagement de GSC dans une voie de différenciation. Les gènes portant la marque répressive dans les GSC-miR-302-367 participent notamment à des catégories fonctionnelles associées à l’expression de propriétés souches et tumorigènes. L’analyse du groupe de gènes portant une marque permissive dans les GSC et répressive dans les GSC-miR-302-367, a révélé un réseau de facteurs de transcription susceptible de participer au contrôle des propriétés souches des GSC. La répression à l’aide de siRNA d’un des membres de ce réseau, le facteur de transcription ARNT2, nous a permis de révéler son rôle dans le maintien des capacités prolifératives des GSC issues de gliomes distincts et dans l’expression du facteur de transcription Nanog, connu pour son rôle central dans le contrôle des propriétés souches des GSC. Nos résultats montrent que l’analyse des changements de marques d’histone offre donc non seulement une vue d’ensemble des différents réseaux moléculaires associés au maintien ou au contraire à la répression des propriétés des GSC, mais permet d’identifier de nouveaux acteurs. L’effet stimulateur d’ARNT2 sur la croissance cellulaire et l’expression de Nanog, dans des GSC dérivées de gliomes différents aux altérations génomiques distinctes, indique que ce facteur de transcription tient une place centrale, insoupçonnée jusqu’à présent, dans la hiérarchie des gènes qui gouvernent les propriétés des GSC. / Gliomas, the most frequent primary brain tumors, are resistant to current therapies and the survival rate of patients is very low. Within high-grade gliomas, a cell sub-population bearing stem-like properties has been isolated. These cells, called glioma stem cell (GSC), are capable of generating all glioma cellular sub-types. Recent data indicates that resistance of these aggressive tumors to therapies is mostly due to GSCs. Thus, targeting the GSCs and their stem-like properties is imperative in order to improve current therapies. [...] Another effective solution to treat GSCs is to force them to lose their stem-like properties. In this context, the aims of my major project were to characterize the epigenetic modifications of histone marks accompanying the loss of GSC stem-like properties under the influence of a cluster of micro-RNA, miR-302-367. GSCs are endowed with an exceptional plasticity, allowing them to gain or lose their stem-like state in response to modifications in their micro-environment. Our results identified the implication of miR-302-367 in the regulation of GSC plasticity. Its stable expression using lentivirus inhibits in an irreversible manner the stem-like and tumorigenic properties of GSC. The tumor-suppressor effect of this miR offers the possibility to decipher the mechanisms responsible for the maintenance or the loss of GSC stem-like properties. Using the model of GSC and their counterparts, GSC-miR-302-367, who lost their stem-like and tumorigenic properties, my aim was to identify the methylation status of histone H3 of the histone code which is known to be associated either to an active or to a repressive gene transcription. I focused on the trimethylation of lysine 4 (H3K4me3) and lysine 27 (H3K27me3), which are associated with an activation or repression of gene transcription, respectively. We performed a ChIP-seq (Chromatin-immunoprecipitation-sequencing) analysis of the respective associated genes followed by a transcriptomic (exon-array) analysis of both cell lines. Our results show that miR-302-367 expression does not alter in a global manner the expression levels of H3K4me3 and H3K27me3. On the contrary, we were able to detect modifications in a discrete group of genes. At least for the studied marks, the positive correlation between the identified histone marks and the gene expression levels indicates that the histone code is well preserved in cancer. GO (Gene Ontology) analysis indicates that miR-302-367-induced loss of stem-like properties is accompanied with activation of the differentiation process in GSC. Genes implicated in the regulation of stem-like and tumorigenic properties were found to bear the repressive histone mark in GSC-miR-302-367. From our analysis of the group of genes bearing the active histone mark in GSC and the repressive one in GSC-miR-302-367, emerged a network of transcription factors that could possibly participate in the regulation of GSC stem-like properties. Down-regulation using siRNA of a member of this network, namely ARNT2, highlighted its role in the maintenance of the proliferative dynamic, as well as the expression of the transcription factor Nanog (a major regulator of GSC stem-like properties), in GSC derived from distinct gliomas. Our histone mark modification analysis, not only elucidated the molecular pathways implicated in the maintenance or, on the contrary, in the loss of GSC stem-like properties, but also, highlighted the implication of new actors in these processes. The activator effect of ARNT2 on GSC proliferation, as well as on the expression of Nanog, observed in GSC bearing distinct genetic alterations and derived from different glioma, indicates that this transcription factor plays a major role, not documented thus far, in the regulation of GSC stem-like properties.

With the advancement of semiconductor technology, the System on Chip (SoC) is becoming more and more complex, so the on-chip communication has become a bottleneck of SoC Design. Since the traditional bus system is inefficient and not scalable, the Network-On-Chip (NoC) has emerged as the promising communication mechanism for complex SoCs. As some systems have specific performance requirements, such as a minimum throughput (for real-time streaming data) or bounded latency (for interrupts, process synchronization, etc), communication with Guaranteed Service (GS) support becomes crucial for predictable SoC architectures. Circuit Switching (CS) is a popular approach to support GS, which firstly has to allocate an exclusively connection (circuit) between the source and destination nodes, and then the data packets are delivered over this connection. However, it is inefficient and inflexible because the resource is occupied by single connection during its whole lifetime, which can block other communications. Hence, two extensions of CS have been proposed to share resources: i) Time-Division Multiplexing (TDM), in which the available link capacity is split into multiple time slots to be shared by different flows in TDM scheme; and ii) Space-Division-Multiplexing (SDM), in which only a subset (sub-channel) of the link wires is exclusively allocated to a specific connection, while the remaining wires of the link can be used by other flows. The connection allocation is critical for CS, since the data delivery can start only after the associated connection is allocated. In this thesis, we propose a dedicated hardware connection allocator to solve the dynamic connection allocation problem for CS NoCs, which has to i) allocate a contention-free path between source-destination pairs and ii) allocate appropriate portions of link bandwidth (appropriate number of time slots and subsets) along the path. The dedicated connection allocator, called NoCManager, solves the connection allocation problem by employing a trellis-search based shortest path algorithm. The trellis search can explore all possible paths between source node and destination. Moreover, it shall find the requested path in a fixed low latency and can guarantee the path optimality in terms of path length if the path is available. In this thesis, two different trellis graphs, Forward-Backtrack trellis and Register-Exchange trellis are proposed. The Forward-Backtrack trellis completes the path search in two steps: forward search and backtracking. Firstly, the forward search begins at source node that traverses the network to find the free path. When destination node is reached, the backtrack starts from destination to select the survivor path and collect the associated path parameters. However, Register-Exchange trellis saves the entire survivor path sequences during forward search. Consequently, the backtracking step can be omitted, and thus the allocation time is halved compared to forward-backtrack approaches. Moreover, each trellis graph consists of three categories, unfolded structure, folded structure and bidirectional structure. The unfolded structure can provide high allocation speed while folded structure is more efficient from a hardware point of view. The bidirectional structure starts the search at two sides, source node and destination node simultaneously, so the allocation speed is 2 times faster than previous unidirectional search. Furthermore, in order to address the scalability issue of previous centralized systems, the partitioned architecture (i.e. spatial partitioning technique) is proposed to divide the large system into multiple smaller differentiated logical partitions served by local NoCManagers. This partitioning technique keeps the request load of the manager and manager-node communication overhead moderate. Inside each partition, the path search problem is solved by a local manager with trellis-search algorithm. To establish a path that crosses partitions, the managers communicate with each other in distributed manner to converge the global path. In order to further enhance the path diversity and resource utilization, we adopt the combined TDM and SDM technique. In combined TDM-SDM approach, each SDM sub-channel is split into multiple time slots so that can be shared by multiple flows. Hence, the number of sub-channels can be kept moderate to reduce router complexity, while still providing higher path diversity than TDM scheme. In order to investigate and optimize TDM-SDM partitioning strategy, we studied the influence of different TDM-SDM link partitioning strategies on success rate and path length that allowed us to find the optimal solution. The dedicated connection allocator using the trellis-search algorithm is employed for TDM, SDM and TDM-SDM CS. In the end, we present the router architecture that combines the circuit-switching network (for GS communication) and packet-switching network (for best-effort communication).

Die umfassende Beobachtbarkeit von System‐on‐Chips (SoCs) ist eine wichtige Voraussetzung für das effiziente Testen und Debuggen eingebetteter Systeme. Ausgehend von einer Analyse verschiedener Anwendungsfälle ergibt sich ein Katalog von Anforderungen an die Beobachtbarkeit von SoCs. Ein wichtiges Kriterium ist hier die Vollständigkeit der Beobachtung und umfasst die Aktivitäten der CPU (ausgeführte Instruktionen, gelesene und geschriebene Daten, Verhalten des Caches, Ausführungszeiten), des Bussystems und von Umgebungsbedingungen. Weitere Kriterien sind die Echtzeitfähigkeit und die Kontinuität der Beobachtung sowie die gleichzeitige Durchführung verschiedener Beobachtungsaufgaben. Dabei soll es zu einer möglichst geringen Beeinflussung des SoCs kommen. Weitere wichtige Aspekt sind die Kosten der Lösung, die Universalität, die Skalierbarkeit sowie die Latenz der Verfügbarkeit der Beobachtungsergebnisse. Für viele Anwendungen, besonders in sicherheitskritischen Bereichen, muss zudem nachgewiesen werden, dass das Beobachtungsverfahren kein Fehlverhalten des SoCs bewirkt bzw. ein solches maskiert. Eine besondere Herausforderung stellen Multiprozessor‐SoCs (MPSoCs) dar, da hier die Kommunikation zwischen den einzelnen CPUs im Inneren des SoC stattfindet und entsprechend schwierig für einen externen Bobachter sichtbar zu machen ist. Der Stand der Technik zur Beobachtung von SoCs wird im Wesentlichen durch zwei Verfahren dargestellt. Bei der Software‐Instrumentierung wird zum funktionalen Programmcode zusätzlicher Code hinzugefügt, welcher zur Beobachtung des Programms dient. Diese Methode ist einfach und universell anwendbar, erfüllt aber die genannten Kriterien nur sehr eingeschränkt. Nachteilig ist hier der Ressourcenverbrauch im Falle des Verbleibs der Instrumentierung im fertigen Produkt. Wird die Instrumentierung nur temporär dem Code hinzugefügt, muss sichergestellt werden, dass das Beobachtungsergebnis auch für den finalen Code anwendbar ist – was besonders bei ressourcen‐abhängigen Integrationstests nur schwierig erfüllbar ist. Eine alternative Lösung stellt eine spezielle Hardware‐Unterstützung in SoCs („embedded Trace“) dar. Hier werden im SoC Zustandsinformationen (z.B. Taskwechsel, ausgeführte Instruktionen, Datentransfers) gesammelt und mittels Trace‐Nachrichten an den Beobachter übermittelt. Dabei stellt die Bandbreite, die zur Ausgabe der Trace‐Nachrichten vom SoC verfügbar ist, ein entscheidendes Nadelöhr dar ‐ im SoC sind viel mehr den Beobachter interessierende Informationen verfügbar als nach außen transferiert werden können. Damit haben beide dem gegenwärtige Stand der Technik entsprechende Beobachtungsverfahren eine Reihe von Einschränkungen, die sich besonders bei der Vollständigkeit der Beobachtung, der Flexibilität, der Kontinuität und der Unterstützung von MPSoCs zeigen. In dieser Arbeit wird nun ein neuer Ansatz vorgestellt, welcher gegenüber dem Stand der Technik in einigen Bereichen deutliche Verbesserungen bietet. Dabei werden die Trace‐Daten nicht vom zu beobachtenden SoC direkt, sondern aus einer parallel mitlaufenden Emulation gewonnen. Die Bandbreite der für die Synchronisation der Emulation erforderlichen Daten ist in vielen Fällen deutlich geringer als bei der Ausgabe von umfassenden Trace‐Nachrichten mittels „embedded Trace“‐Lösungen. Gleichzeitig ist eine vollständige, äußerst detaillierte Beobachtung der Vorgänge innerhalb des SoC möglich. Das neue Beobachtungsverfahren wurde mittels verschiedener FPGA-basierter Implementierungen evaluiert, hier konnte auch die Anwendbarkeit für MPSoCs gezeigt werden.