Digital signal processors and their variants have provided significant benefit to efficient implementation of Physical Layer (PHY) of Open Systems Interconnection (OSI) model’s seven-layer protocol processing stack compared to the general purpose processors. Protocol processors promise to provide a similar advantage for implementing higher layers in the (OSI)'s seven-layer model. This thesis addresses the problem of designing customizable coarse-grain reconfigurable protocol processing fabrics as a solution to achieving high performance and computational efficiency. A key requirement that this thesis addresses is the ability to not only adapt to varying applications and standards, and different modes in each standard but also to time varying load and performance demands while maintaining quality of service.This thesis presents a tile-based multicore protocol processing architecture that can be customized at design time to meet the requirements of the target application. The architecture can then be reconfigured at boot time and tuned to suit the desired use-case. This architecture includes a packet-oriented memory system that has deterministic access time and access energy costs, and hence can be accurately dimensioned to fulfill the requirements of the desired use-case. Moreover, to maintain quality of service as predicted, while minimizing the use of energy and resources, this architecture encompasses an elastic management scheme that controls run-time configuration to deploy processing resources based on use-case and traffic demands.To evaluate the architecture presented in this thesis, different case studies were conducted while quantitative and qualitative metrics were used for assessment. Energy-delay product, energy efficiency, area efficiency and throughput show the improvements that were achieved using the processing cores and the memory of the presented architecture, compared with other solutions. Furthermore, the results show the reduction in latency and power consumption required to evaluate controlling states when using the elastic management scheme. The elasticity of the scheme also resulted in reducing the total area required for the controllers that serve multiple processing cores in comparison with other designs. Finally, the results validate the ability of the presented architecture to support quality of service without misutilizing available energy during a real-life case study of a multi-participant Voice Over Internet Protocol (VOIP) call. / <p>QC 20161028</p>

Delay-tolerant networks (DTNs) are dynamic networks in which senders and receivers are often completely disconnected from each other, often for long periods of time. DTNs are enjoying a burgeoning interest from the research community largely due to the vast potential for meaningful applications, e.g., to enable access to the Internet in remote rural areas, monitor animal behavioral patterns, connect participants in mobile search and rescue applications, provide connectivity in urban environments, and support space communications. Existing work in DTNs generally focuses either on solutions for very specific applications or domains, or on general-purpose protocol-level solutions intended to work across multiple domains. In this proposal, we take a more systems-oriented approach to DTNs. Since applications operating in these dynamic environments would like their connections to be supported by the network technology best suited to the combination of the communication session's requirements and instantaneous network context, we develop a middleware architecture that enables seamless migrations from one communication style to another in response to changing network conditions. We also enable context-awareness in DTNs, using this awareness to adapt communications to more efficiently use network resources. Finally, we explore the systems issues inherent to such a middleware and provide an implementation of it that we test on a mobile computing testbed made up of autonomous robots. / text

Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas com múltiplos processadores num chip (MPSoCs, do inglês MultiProcessor System-on-Chip). Essa possibilidade de integração permite inserir dezenas de Elementos de Processamento (EPs) nos circuitos integrados atuais, e já se projeta centenas de EPs para os sistemas da próxima década (ITRS, 2011). Nesse cenário, um dos principais desafios se refere ao serviço de interconexão dos EPs, que deve apresentar um desempenho de comunicação necessário para as aplicações em execução sem comprometer as limitações de consumo de área e energia do circuito. Nos primeiros sistemas multiprocessados, com poucos nodos, arquiteturas baseadas em barramento foram suficientes para cumprir esses requisitos. Porém, o número de elementos nos sistemas recentes aumentou rapidamente, tornando as redes-em-chip a solução mais apropriada, por aliar escalabilidade e reuso na mesma estrutura. Contudo, diante da previsão de que essa tendência de aumento se manterá retorna a discussão se as redes-em-chip atuais continuarão adequadas para os futuros sistemas. De fato, o custo das redes-em-chip convencionais pode se tornar proibitivo para as escalas dos circuitos em um futuro próximo. Novas propostas têm sido apresentadas na literatura científica onde se podem destacar duas principais estratégias de projeto às redes de interconexão: reconfiguração arquitetural e organização hierárquica da topologia. A reconfiguração arquitetural permite obter uma grande eficiência, independente do tipo de aplicação em execução, pois uma das alternativas é projetar o circuito para que ele se auto adapte conforme os requisitos de desempenho para cada aplicação. Por outro lado, arquiteturas organizadas em topologias hierárquicas são desenvolvidas para uma estrutura computacional definida em tempo de projeto, sendo mais eficazes para uma classe de aplicações. O presente trabalho explora a sinergia da combinação das potencialidades das duas soluções e propõe uma nova estrutura que oferece melhor desempenho para uma classe maior de aplicações apropriada para os futuros sistemas. Como resultado foi implementada uma arquitetura adaptativa chamada MINoC (Multiple Interconnections Networks-on-Chip), uma arquitetura organizada em hierarquia, chamada HiCIT (Hierarchical Crossbar-based Interconnection Topology) e uma simbiose de ambas culminando na arquitetura hierárquica adaptativa HASIN (Hierarchical Adaptive Switching Interconnection Network). São apresentados resultados que mostram a eficiência desses conceitos validando a proposta hierárquica adaptativa. / With the advent of submicron processes, the number of transistors integrated on a single chip has reached levels that allowed the design of Multiprocessor Systems-on-Chip (MPSoCs). This capability allows the integration of several processing elements (PEs) in integrated circuits designed nowadays. In the next decade it is expected that hundreds of PEs will be integrated on a single chip. In this scenario, a key challenge is the interconnection network between PEs, which must provide the communication service required to run applications without compromising the limitations of area and energy consumption. In the first multiprocessor systems, with few nodes, bus-based approaches have been sufficient to meet these requirements. However, current systems increased quickly the number of elements, making the Networks-on-Chip (NoCs) the most appropriate solution, because it handles scalability and reusability in the same structure. Nevertheless, ITRS roadmap predicts that this increase will continue (ITRS, 2011), which resumes the discussion if present NoC architectures will be the most adequate for future systems, since its costs could be prohibitive. Therefore, new proposals have been presented in the literature with two main design strategies: architectural reconfiguration and hierarchical organization of the topology. With the architectural reconfiguration it is possible to obtain an application independent high efficiency structure, because the circuit is designed to adapt itself to satisfy performance requirements. On the other hand, architectural organizations in hierarchical topologies are defined at design time to have the most appropriate features for a class of applications, being very effective. The current work identified the synergy of both approaches and proposes a new symbiotic structure suitable for a broader class of applications. As a result, it was implemented an adaptive architecture called MINoC (Multiple Interconexions Networks-on-chip), an architecture organized in hierarchy called HiCIT (Hierarchical Crossbar-based Interconnection Topology) and a mix of both ending up with the hierarchical adaptive architecture HASIN (Hierarchical Interconnection Network Adaptive Switching). Results show the efficiency of these concepts validating the proposed hierarchical adaptive architecture.

Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas com múltiplos processadores num chip (MPSoCs, do inglês MultiProcessor System-on-Chip). Essa possibilidade de integração permite inserir dezenas de Elementos de Processamento (EPs) nos circuitos integrados atuais, e já se projeta centenas de EPs para os sistemas da próxima década (ITRS, 2011). Nesse cenário, um dos principais desafios se refere ao serviço de interconexão dos EPs, que deve apresentar um desempenho de comunicação necessário para as aplicações em execução sem comprometer as limitações de consumo de área e energia do circuito. Nos primeiros sistemas multiprocessados, com poucos nodos, arquiteturas baseadas em barramento foram suficientes para cumprir esses requisitos. Porém, o número de elementos nos sistemas recentes aumentou rapidamente, tornando as redes-em-chip a solução mais apropriada, por aliar escalabilidade e reuso na mesma estrutura. Contudo, diante da previsão de que essa tendência de aumento se manterá retorna a discussão se as redes-em-chip atuais continuarão adequadas para os futuros sistemas. De fato, o custo das redes-em-chip convencionais pode se tornar proibitivo para as escalas dos circuitos em um futuro próximo. Novas propostas têm sido apresentadas na literatura científica onde se podem destacar duas principais estratégias de projeto às redes de interconexão: reconfiguração arquitetural e organização hierárquica da topologia. A reconfiguração arquitetural permite obter uma grande eficiência, independente do tipo de aplicação em execução, pois uma das alternativas é projetar o circuito para que ele se auto adapte conforme os requisitos de desempenho para cada aplicação. Por outro lado, arquiteturas organizadas em topologias hierárquicas são desenvolvidas para uma estrutura computacional definida em tempo de projeto, sendo mais eficazes para uma classe de aplicações. O presente trabalho explora a sinergia da combinação das potencialidades das duas soluções e propõe uma nova estrutura que oferece melhor desempenho para uma classe maior de aplicações apropriada para os futuros sistemas. Como resultado foi implementada uma arquitetura adaptativa chamada MINoC (Multiple Interconnections Networks-on-Chip), uma arquitetura organizada em hierarquia, chamada HiCIT (Hierarchical Crossbar-based Interconnection Topology) e uma simbiose de ambas culminando na arquitetura hierárquica adaptativa HASIN (Hierarchical Adaptive Switching Interconnection Network). São apresentados resultados que mostram a eficiência desses conceitos validando a proposta hierárquica adaptativa. / With the advent of submicron processes, the number of transistors integrated on a single chip has reached levels that allowed the design of Multiprocessor Systems-on-Chip (MPSoCs). This capability allows the integration of several processing elements (PEs) in integrated circuits designed nowadays. In the next decade it is expected that hundreds of PEs will be integrated on a single chip. In this scenario, a key challenge is the interconnection network between PEs, which must provide the communication service required to run applications without compromising the limitations of area and energy consumption. In the first multiprocessor systems, with few nodes, bus-based approaches have been sufficient to meet these requirements. However, current systems increased quickly the number of elements, making the Networks-on-Chip (NoCs) the most appropriate solution, because it handles scalability and reusability in the same structure. Nevertheless, ITRS roadmap predicts that this increase will continue (ITRS, 2011), which resumes the discussion if present NoC architectures will be the most adequate for future systems, since its costs could be prohibitive. Therefore, new proposals have been presented in the literature with two main design strategies: architectural reconfiguration and hierarchical organization of the topology. With the architectural reconfiguration it is possible to obtain an application independent high efficiency structure, because the circuit is designed to adapt itself to satisfy performance requirements. On the other hand, architectural organizations in hierarchical topologies are defined at design time to have the most appropriate features for a class of applications, being very effective. The current work identified the synergy of both approaches and proposes a new symbiotic structure suitable for a broader class of applications. As a result, it was implemented an adaptive architecture called MINoC (Multiple Interconexions Networks-on-chip), an architecture organized in hierarchy called HiCIT (Hierarchical Crossbar-based Interconnection Topology) and a mix of both ending up with the hierarchical adaptive architecture HASIN (Hierarchical Interconnection Network Adaptive Switching). Results show the efficiency of these concepts validating the proposed hierarchical adaptive architecture.

Com o advento dos processos submicrônicos, a capacidade de integração de transistores numa mesma pastilha de silício atingiu níveis que possibilitaram a construção dos sistemas com múltiplos processadores num chip (MPSoCs, do inglês MultiProcessor System-on-Chip). Essa possibilidade de integração permite inserir dezenas de Elementos de Processamento (EPs) nos circuitos integrados atuais, e já se projeta centenas de EPs para os sistemas da próxima década (ITRS, 2011). Nesse cenário, um dos principais desafios se refere ao serviço de interconexão dos EPs, que deve apresentar um desempenho de comunicação necessário para as aplicações em execução sem comprometer as limitações de consumo de área e energia do circuito. Nos primeiros sistemas multiprocessados, com poucos nodos, arquiteturas baseadas em barramento foram suficientes para cumprir esses requisitos. Porém, o número de elementos nos sistemas recentes aumentou rapidamente, tornando as redes-em-chip a solução mais apropriada, por aliar escalabilidade e reuso na mesma estrutura. Contudo, diante da previsão de que essa tendência de aumento se manterá retorna a discussão se as redes-em-chip atuais continuarão adequadas para os futuros sistemas. De fato, o custo das redes-em-chip convencionais pode se tornar proibitivo para as escalas dos circuitos em um futuro próximo. Novas propostas têm sido apresentadas na literatura científica onde se podem destacar duas principais estratégias de projeto às redes de interconexão: reconfiguração arquitetural e organização hierárquica da topologia. A reconfiguração arquitetural permite obter uma grande eficiência, independente do tipo de aplicação em execução, pois uma das alternativas é projetar o circuito para que ele se auto adapte conforme os requisitos de desempenho para cada aplicação. Por outro lado, arquiteturas organizadas em topologias hierárquicas são desenvolvidas para uma estrutura computacional definida em tempo de projeto, sendo mais eficazes para uma classe de aplicações. O presente trabalho explora a sinergia da combinação das potencialidades das duas soluções e propõe uma nova estrutura que oferece melhor desempenho para uma classe maior de aplicações apropriada para os futuros sistemas. Como resultado foi implementada uma arquitetura adaptativa chamada MINoC (Multiple Interconnections Networks-on-Chip), uma arquitetura organizada em hierarquia, chamada HiCIT (Hierarchical Crossbar-based Interconnection Topology) e uma simbiose de ambas culminando na arquitetura hierárquica adaptativa HASIN (Hierarchical Adaptive Switching Interconnection Network). São apresentados resultados que mostram a eficiência desses conceitos validando a proposta hierárquica adaptativa. / With the advent of submicron processes, the number of transistors integrated on a single chip has reached levels that allowed the design of Multiprocessor Systems-on-Chip (MPSoCs). This capability allows the integration of several processing elements (PEs) in integrated circuits designed nowadays. In the next decade it is expected that hundreds of PEs will be integrated on a single chip. In this scenario, a key challenge is the interconnection network between PEs, which must provide the communication service required to run applications without compromising the limitations of area and energy consumption. In the first multiprocessor systems, with few nodes, bus-based approaches have been sufficient to meet these requirements. However, current systems increased quickly the number of elements, making the Networks-on-Chip (NoCs) the most appropriate solution, because it handles scalability and reusability in the same structure. Nevertheless, ITRS roadmap predicts that this increase will continue (ITRS, 2011), which resumes the discussion if present NoC architectures will be the most adequate for future systems, since its costs could be prohibitive. Therefore, new proposals have been presented in the literature with two main design strategies: architectural reconfiguration and hierarchical organization of the topology. With the architectural reconfiguration it is possible to obtain an application independent high efficiency structure, because the circuit is designed to adapt itself to satisfy performance requirements. On the other hand, architectural organizations in hierarchical topologies are defined at design time to have the most appropriate features for a class of applications, being very effective. The current work identified the synergy of both approaches and proposes a new symbiotic structure suitable for a broader class of applications. As a result, it was implemented an adaptive architecture called MINoC (Multiple Interconexions Networks-on-chip), an architecture organized in hierarchy called HiCIT (Hierarchical Crossbar-based Interconnection Topology) and a mix of both ending up with the hierarchical adaptive architecture HASIN (Hierarchical Interconnection Network Adaptive Switching). Results show the efficiency of these concepts validating the proposed hierarchical adaptive architecture.

Oil is a finite resource; This much has been established as fact and is commonly agreed upon. We will, some day, find our supplies depleted. The question that remains hotly debated, however, is when this will happen and what impacts it will have on our modern lives. Estimates and forecasts abound, but still no one can answer these questions definitively. As fossil fuels, the energy behind virtually every aspect of our lives, become scarce, our patterns of growth will face a reckoning. We will be forced to adapt and adjust; either shifting our energy demand to more renewable sources, or reducing it by significant amounts. Although there are a plethora of what-if scenarios when predicting the effects of an end to oil, it’s easy to recognize that the peak oil crisis will significantly impact our lives. It will change how we live them and, by extension, where and how we construct our buildings. So what does this mean for buildings - one of the country’s largest consumers of energy? This thesis proposes that a theory of adaptability, when applied properly to the design and construction process, can begin to equip our building to handle the range of possible outcomes that an energy-poor future poses. This thesis also aims to address, in the broadest of terms, how our current approach to design could lead to significant issues in a post-oil, energy hungry world. It does so by encouraging a more holistic approach to problem solving and building design, while outlining how the values of cost efficiency and speed have polarized global construction techniques.

Dans le contexte du développement de systèmes embarqués alliant hautes performances et basse consommation, la recherche de l'efficacité énergétique optimale des processeurs est devenue un défi majeur. Les solutions architecturales se sont positionnées durant les dernières décennies comme d'importantes contributrices à ce challenge. Ces solutions, permettant la gestion du compromis performance de calcul/consommation, se sont dans un premier temps développées pour les circuits mono-processeurs. Elles évoluent aujourd'hui pour s'adapter aux contraintes de circuits MPSoCs de plus en plus complexes et sensibles aux déviations des procédés de fabrication, aux variations de tension et de température. Cette variabilité limite aujourd'hui drastiquement l'efficacité énergétique de chacune des unités de calcul qui composent une architecture MPSoC, car des marges pessimistes de fonctionnement sont généralement prises en compte. De grandes améliorations peuvent être attendues de la diminution de ces marges de fonctionnement en surveillant dynamiquement et localement la variabilité de chaque unité de calcul afin de réajuster ses paramètres de fonctionnement tension/fréquence. Ce travail s'insère dans une solution architecturale bas-coût nommée AVFS, basée sur une optimisation des techniques de gestion locales DVFS, permettant de réduire les marges de conception afin d'améliorer l'efficacité énergétique des MPSoCs, tout en minimisant l'impact de la solution proposée sur la surface de silicium et l'énergie consommée. Le développement d'un système de surveillance des variations locales et dynamiques de la tension et de la température à partir d'un capteur bas coût a été proposé. Une première méthode permet d'estimer conjointement la tension et la température à l'aide de tests statistiques. Une seconde permet d'accélérer l'estimation de la tension. Enfin, une méthode de calibration associée aux deux méthodes précédentes a été développée. Ce système de surveillance a été validé sur une plateforme matérielle afin d'en démontrer le caractère opérationnel. En prenant en compte les estimées de tension et de température, des politiques visant à réajuster dynamiquement les consignes des actionneurs locaux de tension et de fréquence ont été proposées. Finalement, la consommation additionnelle due à l'intégration des éléments constitutifs de l'architecture AVFS a été évaluée et comparée aux réductions de consommation atteignables grâce aux réductions des marges de fonctionnement. Ces résultats ont montré que la solution AVFS permet de réaliser des gains en consommation substantiels par rapport à une solution DVFS classique. / Nowadays, embedded systems requiring high performance and low power, the search for the optimal efficiency of the processors has become a major challenge. Architectural solutions have positioned themselves in recent decades as one of the main contributors to this challenge. These solutions enable the management of the trade-off between performance / power consumption, initially developed for single -processor systems. Today, they evolve to be adapted to the constraints of circuits MPSoCs increasingly complex and sensitive to process, voltage and temperature variations. This PVT variability limits drastically the energy efficiency of each of the processing units of a MPSoC architecture, taking into account pessimistic operating margins. Significant improvements can be expected from the reduction of the operating margins by dynamically monitoring and local variability of each resource and by adjusting its voltage / frequency operating point. This work is part of a low-cost architectural solution called AVFS, based on local DVFS optimization technique, to reduce design margins and improve the energy efficiency of MPSoCs, while minimizing the silicon surface and the energy additional cost. The development of a monitoring system of local and dynamic voltage and temperature variations using a low-cost sensor has been proposed. A first method estimates jointly voltage and temperature using statistical tests. A second one speeds up estimation of the voltage. Finally, a calibration method associated with the two previous methods has been developed. This monitoring system has been validated on a hardware platform to demonstrate its operational nature. Taking into account the estimation of voltage and temperature values, policies to dynamically adjust the set point of the local voltage and frequency actuators have been proposed. Finally, the additional power consumption due to the integration of the components of the architecture AVFS was evaluated and compared with reductions achievable through reductions in operating margins consumption. These results showed that the AVFS solution can achieve substantial power savings compared to conventional DVFS solution.

La réduction des dimensions des transistors a augmenté la sensibilité des circuits numériques aux variations PVT et, plus récemment, aux effets de vieillissement, notamment BTI et HCI. De larges marges de sécurité sont donc nécessaires pour assurer un fonctionnement correct du circuit, ce qui entraîne une perte d'énergie importante. Les solutions actuelles pour améliorer l'efficacité énergétique sont principalement basées sur des solutions de type «Adaptive Voltage and Frequency Scaling (AVFS)». Cependant, ce type de solution ne peut anticiper les variations avant qu'elles ne se produisent. Cette approche doit donc être amélioré pour traiter les problèmes de fiabilité liés au vieillissement. Cette thèse propose une nouvelle méthodologie pour générer des modèles simplifiés pour estimer la fréquence maximale du circuit Fmax. Un premier modèle est créé pour estimer le délai de propagation du (des) chemin(s) critique(s) en fonction des variations PVT. Les effets BTI et HCI sont ensuite modélisés via une modification des paramètres du premier modèle. Construit à partir des modèles au niveau transistor, le modèle de vieillissement obtenu prend en compte tous les facteurs qui influent sur le vieillissement, à savoir, la topologie des circuits, l'application, la tension et la température. La méthodologie proposée est validée sur deux architectures en technologie 28nm FD-SOI. Les modèles peuvent être alimentés par des moniteurs de température et de tension, ce qui permet une évaluation précise de l'évolution de Fmax. Toutefois, ces moniteurs sont sensibles au vieillissement. Aussi, une méthode de recalibrage pour compenser les effets du vieillissement a été développée pour un moniteur numérique de température et de tension. Des exemples d'applications en ligne sont donnés. Les modèles sont également utilisés pour simuler des circuits complexes sous des variations de vieillissement, par exemple un circuit multi-cœur et un système AVFS. Cela permet d'évaluer différentes stratégies concernant la performance, l'énergie et la fiabilité. / The continuous scaling of transistor dimensions has increased the sensitivity of digital circuits to PVT variations and, more recently, to aging effects such as BTI and HCI. Large voltage guard bands, corresponding to worst-case operation, are thus necessary and leads to a considerable energy loss. Current solutions to increase energy efficiency are mainly based on Adaptive Voltage and Frequency Scaling (AVFS). However, as a reactive solution, it cannot anticipate the variation before it occurs. It has, thus, to be improved for handling long-term reliability issues. This thesis proposes a new methodology to generate simplified but nevertheless accurate models to estimate the circuit maximum operating frequency Fmax. A first model is created for the modelling of the propagation delay of the critical path(s) as a function of PVT variations. Both BTI/HCI effects are then modelled as a shift in the parameters of the first model. Built on the top of device-level models, it takes into account all factors that impact global aging, namely, circuit topology, workload, voltage and temperature variations. The proposed modelling approach is evaluated on two architectures implemented in 28nm FD-SOI technology. The models can be fed by temperature and voltage monitors. This allows an accurate assessment of the circuit Fmax evolution during its operation. However, these monitors are prone to aging. Therefore, an aging-aware recalibration method has been developed for a particular V T monitor. Examples of on-line applications are given. Finally, the models are used to simulate complex circuits under aging variations such a multi-core circuit and an AVFS system. This allows the evaluation of different strategies regarding performance, energy and reliability.

Malgré des avantages certains en terme d'adaptabilité et en gain de surface, la reconfiguration dynamique sur FPGA a du mal à être utilisée dans l'industrie. Le manque de moyens et de méthodes d'évaluation d'une telle architecture en est la cause majeure. Pire, aucun outil officiel ne permet aux développeurs de déterminer facilement un ordonnancement de la reconfiguration adapté pour une architecture donnée. Cette thèse s'inscrit dans ce contexte et propose une méthodologie de modélisation SystemC d'architectures reconfigurables dynamiquement. Cet outil d'aide à la conception permet de faire gagner un temps considérable lors de la phase de conception en fournissant une première estimation des performances et des ressources nécessaires au développement de l'architecture. Il permet également le développement et la validation de scénarios d'ordonnancement de la reconfiguration, tout en respectant les contraintes temps réel liées à l'application. Afin de valider notre modèle sur une application réelle, des IP de transcodage vidéo ont été développées et seront détaillées. Cette application consiste en la réalisation d'un transcodeur H.264/MPEG-2, rendu auto-adaptable grâce à l'utilisation de la reconfiguration dynamique. Ces travaux ont été menés dans le cadre du projet ARDMAHN financé par l'Agence Nationale de la Recherche portant la référence ANR-09-SEGI-001 / Despite clear benefits in terms of fexibility and surface efficiency, dynamic reconfiguration of FPGAs is still finding it hard to break through into massive industrial project. One of the main reasons is the lack of means and methods for evaluation of reconfigurable architectures. Worse, main FPGA vendors do not provide official tools allowing developers to easily determine an optimal scheduling reconfiguration for a specific architecture. Within this framework, the proposed research work described in this thesis proposes a methodology for modeling dynamically reconfigurable architectures based on SystemC. The proposed methodology allows designers to save significant time during the design phases of an application specific reconfigurable architecture by providing an initial estimate of performance and resources needed for its development. It also allows development and validation of scheduling reconfiguration scenarios, while respecting real-time constraints associated with the given application. To validate our methodology on a real application, video transcoding IP have been developed and tested. This application consists in the realization of a H.264/MPEG-2 transcoder made self-adaptable through the use of dynamic reconfiguration. This work was conducted as a part of the ARDMAHN project sponsored by the National Research Agency (Agence Nationale de Recheche) with the reference number ANR-09-SEGI-001

Les architectures reconfigurables à base de FPGA sont capables de fournir des solutions adéquates pour plusieurs applications vu qu'elles permettent de modifier le comportement d'une partie du FPGA pendant que le reste du circuit continue de s'exécuter normalement. Ces architectures, malgré leurs progrès, souffrent encore de leur manque d'adaptabilité fasse à des applications constituées de tâches matérielles de taille différente. Cette hétérogénéité peut entraîner de mauvais placements conduisant à une utilisation sous-optimale des ressources et par conséquent une diminution des performances du système. La contribution de cette thèse porte sur la problématique du placement des tâches matérielles de tailles différentes et de la génération efficace des régions reconfigurables. Une méthodologie et une couche intermédiaire entre le FPGA et l'application sont proposées pour permettre le placement efficace des tâches matérielles de tailles différentes sur des partitions reconfigurables de taille prédéfinie. Pour valider la méthode, on propose une architecture basée sur l'utilisation de la reconfiguration partielle afin d'adapter le transcodage d'un format de compression vidéo à un autre de manière souple et efficace. Une étude sur le partitionnement de la région reconfigurable pour les tâches matérielles de l'encodeur entropique (CAVLC / VLC) est proposée afin de montrer l'apport du partitionnement. Puis une évaluation du gain obtenu et du surcoût de la méthode est présentée / FPGA-based reconfigurable architectures can deliver appropriate solutions for several applications as they allow for changing the performance of a part of the FPGA while the rest of the circuit continues to run normally. These architectures, despite their improvements, still suffer from their lack of adaptability when confronted with applications consisting of variable size material tasks. This heterogeneity may cause wrong placements leading to a sub-optimal use of resources and therefore a decrease in the system performances. The contribution of this thesis focuses on the problematic of variable size material task placement and reconfigurable region effective generation. A methodology and an intermediate layer between the FPGA and the application are proposed to allow for the effective placement of variable size material tasks on reconfigurable partitions of a predefined size. To approve the method, we suggest an architecture based on the use of partial reconfiguration in order to adapt the transcoding of one video compression format to another in a flexible and effective way. A study on the reconfigurable region partitioning for the entropy encoder material tasks (CAVLC / VLC) is proposed in order to show the contribution of partitioning. Then an assessment of the gain obtained and of the method additional costs is submitted