La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo de coherencia. La cantidad de trafico, el porcentaje de mensajes cortos y largos y el patrón de trafico en general varían dependiendo de la geometría de las caches y del protocolo de coherencia. La arquitectura de la NoC y la jerarquía de caches están de hecho firmemente acopladas, y estos dos componentes deben ser diseñados y evaluados conjuntamente para estudiar como el variar uno afecta a las prestaciones del otro. Además, cada componente debe ajustarse a los requisitos y a las oportunidades del otro, y al revés. Normalmente diferentes clases de mensajes se envían por diferentes redes virtuales o por NoCs con diferente ancho de banda, separando mensajes largos y cortos. Sin embargo, otra clasificación de los mensajes se puede hacer dependiendo del tipo de información que proveen: algunos mensajes, como las peticiones de datos, necesitan campos para almacenar información (dirección del bloque, tipo de petición, etc.); otros, como los mensajes de reconocimiento (ACK), no proporcionan ninguna información excepto por el ID del nodo destino: solo proveen una información de tipo temporal, en el sentido que la recepción de un ACK indica que el nodo fuente ha recibido el mensaje al que está contestando con el ACK y completado todas las operaciones determinadas por el protocolo de coherencia. Esta segunda clase de mensaje no necesita de mucho ancho de banda: la latencia es mucho mas importante, dado que el nodo destino esta típicamente bloqueado esperando la recepción de ellos. En este trabajo de tesis se desarrolla una red dedicada para trasmitir la segunda clase de mensajes; la red es muy sencilla y rápida, y permite la entrega de los ACKs con una latencia de pocos ciclos de reloj. Reduciendo la latencia y el trafico en la NoC debido a los ACKs, es posible: -acelerar la fase de invalidación en fase de escritura en un sistema que usa un protocolo de coherencia basado en directorios -mejorar las prestaciones de un protocolo de coerencia basado en broadcast, hasta llegar a prestaciones comparables con las de un protocolo de directorios pero sin el coste de área debido a la necesidad de almacenar el directorio -implementar un mapeado dinámico de bloques a las caches de ultimo nivel de forma eficiente, con el objetivo de acercar cuanto al máximo los bloques a los cores que los utilizan El objetivo final es obtener un co-diseño de NoC y jerarquía de caches que minimice los problemas de escalabilidad de los protocolos de coherencia. Como gran objetivo final, se pretende la implementación de un CMP con ubicación dinámica de los recursos de cache y red, tal que estos recursos se puedan particionar de forma eficiente e independiente para asignar diferentes particiones a diferentes aplicaciones en un entorno virtualizado. / Lodde, M. (2014). Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/35325

Several trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, emerging applications such as streaming media and on-line transaction processing have shown greater thread-level parallelism. Finally, the increasing gap between processor and off-chip memory speeds has constrained performance of memory-intensive applications. The Single-Chip Message Passing (SCMP) parallel computer sits at the confluence of these trends. SCMP is a tiled architecture consisting of numerous thread-parallel processor and memory nodes connected through a structured interconnection network. Using an interconnection network removes global, ad-hoc wiring that limits scalability and introduces design complexity. However, routing data through general purpose interconnection networks can come at the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. Understanding the impact architectural decisions have on cost and performance will aid in the eventual adoption of general purpose interconnects. This thesis covers the design and analysis of the on-chip network and its integration with the SCMP system. The result of these efforts is a framework for analyzing on-chip interconnection networks that considers network performance, circuit area, and power consumption. / Master of Science

京都大学 / 新制・課程博士 / 博士(工学) / 甲第24812号 / 工博第5155号 / 新制||工||1985(附属図書館) / 京都大学大学院工学研究科マイクロエンジニアリング専攻 / (主査)教授 横川 隆司, 教授 安達 泰治, 教授 永樂 元次 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DGAM

[ES] En este trabajo se ha realizado la detección de analitos implicados en el sector sanitario (trombina) e industria alimentaria (alérgenos y patógenos), mediante el uso de un sistema de biosensado fotónico. Este sistema desarrollado por el equipo de LUMENSIA Sensors, emplea la tecnología de chips fotónicos de nitruro de silicio (Si3N4), basados en estructuras de anillos resonantes (RR). Las estrategias de funcionalización química e inmovilización de biomoléculas como aptámeros (fragmentos de ADN de cadena sencilla) y anticuerpos, se han realizado sobre superficies planas de Si3N4 para la detección de analitos, como paso previo a las medidas fotónicas. Por tanto, estas estrategias se han implementado en la preparación del chip fotónico para las medidas en un entorno de laboratorio (set-up). En cuanto a la estrategia aplicada, ésta consiste en la activación química de la superficie del sensor. Después sobre los RR del chip, cuyo tamaño es del orden de las micras, se inmoviliza la sonda de captura (anticuerpo o aptámero), siendo ésta la encargada de reconocer específicamente al analito de interés (trombina, alérgeno o patógeno). En los resultados obtenidos de trombina, se ha elaborado un estudio para la detección de trombina en el seno de diferentes matrices biológicas sobre superficies planas de Si3N4, además del control sobre la activación de una muestra de sangre mediante el uso de factor tisular (TF) y cloruro de calcio (CaCl2). Estos resultados han servido como un estudio preliminar a la optimización del aptámero empleado como sonda de captura, específico de la trombina para su detección sobre chips fotónicos. En lo referente a la detección de alérgenos, se han empleado dos estrategias claramente diferenciadas. Por un lado, la utilización de aptámeros como sondas de captura en la detección del Ovomucoide (OVO) y la Gliadina (GLN) sobre superficies planas Si3N4. Por otro lado, la implementación de anticuerpos monoclonales como moléculas biológicas de captura sobre chips fotónicos, se ha llevado a cabo en la detección de los alérgenos Gliadina (GLN) y caseína (CAS), cuyos resultados han dado lugar a una recta de calibrado. Asimismo, se ha realizado un ensayo para la detección de GLN en muestra real, procedente de un extracto cárnico con gluten de trigo. En cuanto a la detección de patógenos, se han utilizado dos tipos de estrategias, al igual que para los alérgenos. En primer lugar, el uso de aptámeros como sondas de captura han dado como resultado la detección de dos cepas de carácter no patogénico de la bacteria E.coli (Origami y XL1BLUE) sobre superficies planas de Si3N4. En segundo lugar, la utilización de un anticuerpo policlonal como sonda de captura, se ha inmovilizado sobre la superficie del chip fotónico para la detección del Circovirus Porcino tipo 2 (PCV2) en un estudio realizado sobre la dosis dependencia del virus a diferentes factores de dilución. Finalmente, el desarrollo de una plataforma de sensado para la detección de los analitos (trombina, alérgenos y patógenos) y donde se vayan a implementar los diferentes biosensores está en proceso. / [CA] En aquest treball s'ha realitzat la detecció d'anàlits implicats en el sector sanitari (trombina) i indústria alimentària (al·lergògens i patògens), mitjançant l'ús d'un sistema de biosensat fotònic. Aquest sistema desenvolupat per l'equip de LUMENSIA Sensors, empra la tecnologia de xips fotònics de nitrur de silici (Si3N4), basats en estructures d'anells ressonants (RR). Les estratègies de funcionalització química i immobilització de biomolècules com aptàmers (fragments d'ADN de cadena senzilla) i anticossos, s'han realitzat sobre superfícies planes de Si3N4 per a la detecció d'anàlits, com a pas previ a les mesures fotòniques. Per tant, aquestes estratègies s'han implementat en la preparació del xip fotònic per a les mesures en un entorn de laboratori (set-up). Quant a l'estratègia aplicada, aquesta consisteix en l'activació química de la superfície del sensor. Després sobre els RR del xip, la grandària del qual és de l'ordre de les micres, s'immobilitza la sonda de captura (anticòs o aptàmer), sent aquesta l'encarregada de reconèixer específicament a l'anàlit d'interés (trombina, al·lergogen o patogen). En els resultats obtinguts de trombina, s'ha elaborat un estudi per a la detecció de trombina en el si de diferents matrius biològiques sobre superfícies planes de Si3N4, a més del control sobre l'activació d'una mostra de sang mitjançant l'ús de factor tissular (TF) i clorur de calci (CaCl2). Aquests resultats han servit com un estudi preliminar a l'optimització del aptàmer empleat com sonda de captura, específic de la trombina per a la seua detecció sobre xips fotònics. Referent a la detecció d'al·lergògens, s'han emprat dues estratègies clarament diferenciades. D'una banda, la utilització de aptàmers com sondes de captura en la detecció del Ovomucoide (OVO) i la Gliadina (GLN) sobre superfícies planes Si3N4. D'altra banda, la implementació d'anticossos monoclonals com a molècules biològiques de captura sobre xips fotònics, s'ha dut a terme en la detecció dels al·lergògens Gliadina (GLN) i caseïna (CAS), els resultats de la qual han donat lloc a una recta de calibrat. Així mateix, s'ha realitzat un assaig per a la detecció de GLN en mostra real, procedent d'un extracte carni amb gluten de blat. Quant a la detecció de patògens, s'han utilitzat dos tipus d'estratègies, igual que per als al·lergògens. En primer lloc, l'ús de aptàmers com sondes de captura han donat com a resultat la detecció de dos ceps de caràcter no patogènic del bacteri E.coli (Origami i XL1BLUE) sobre superfícies planes de Si3N4. En segon lloc, la utilització d'un anticòs policlonal com sonda de captura, s'ha immobilitzat sobre la superfície del xip fotònic per a la detecció del Circovirus Porcí tipus 2 (PCV2) en un estudi realitzat sobre la dosi dependència del virus a diferents factors de dilució. Finalment, el desenvolupament d'una plataforma de sensat per a la detecció dels anàlits (trombina, al·lergògens i patògens) i on es vagen a implementar els diferents biosensors està en procés. / [EN] In this work the detection of analytes involved in the health sector (thrombin) and food industry (allergens and pathogens) has been carried out, through the use of a photonic biosensing system. This system, developed by the LUMENSIA Sensors team, uses the technology of silicon nitride (Si3N4) photonic chips, based on resonant ring structures (RR). The strategies of chemical functionalization and immobilization of biomolecules such as aptamers (single chain DNA fragments) and antibodies, have been performed on flat surfaces of Si3N4 for the detection of analytes, as a previous step to photonic measurements. Therefore, these strategies have been implemented in the preparation of the photonic chip for measurements in a laboratory environment (set-up). Refering to the strategy applied, it consists of the chemical activation of the sensor surface. Then on the RR of the chip, whose size is of the order of microns, the capture probe (antibody or aptamer) is immobilized, being the one in charge of specifically recognizing the analyte of interest (thrombin, allergen or pathogen). In the results obtained from thrombin, a study for the detection of thrombin in different biological matrices on flat surfaces of Si3N4 has been developed, in addition to the control on the activation of a blood sample through the use of tissue factor (TF) and calcium chloride (CaCl2). These results have served as a preliminary study to the optimization of the aptamer used as a capture probe, specific for thrombin for detection on photonic chips. Regarding the detection of allergens, two clearly differentiated strategies have been used. On the one hand, the use of aptamers as capture probes in the detection of Ovomucoid (OVO) and Gliadin (GLN) on Si3N4 flat surfaces. On the other hand, the implementation of monoclonal antibodies as biological capture molecules on photonic chips has been carried out in the detection of the allergens Gliadina (GLN) and casein (CAS), whose results have resulted in a calibration line. Likewise, an assay for the detection of GLN in real sample, from a meat extract with wheat gluten, has been carried out. As for the detection of pathogens, two types of strategies have been used, as for allergens. First, the use of aptamers as capture probes has resulted in the detection of two non-pathogenic strains of the E.coli bacteria (Origami and XL1BLUE) on flat surfaces of Si3N4. Secondly, the use of a polyclonal antibody as a capture probe has been immobilized on the surface of the photonic chip for the detection of Porcine Circovirus type 2 (PCV2) in a study on the dose dependence of the virus at different dilution factors. Finally, the development of a sensing platform for the detection of analytes (thrombin, allergens and pathogens) and where the different biosensors are going to be implemented is in process. / Quiero agradecer al Instituto de Salud Carlos III por el contrato i-PFIS concedido / Sánchez Sánchez, C. (2019). Sistema de biosensado fotónico para la detección de trombina, alérgenos y patógenos. funcionalización química de chips fotónicos basados en estructuras de anillos resonantes [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/133060

System-on-chips (SoCs) have become fundamental components in modern electronic devices, from low-power microcontrollers to high-performance AI computing systems. With the increasing demand for performance and efficiency, innovative approaches in power management and clocking mechanisms are increasingly important. One such approach combines multiple regulator architectures to form a hybrid voltage regulation, which this work demonstrated with buck converters and digital low-dropout (D-LDO) regulators. Additionally, the increasing demand for sub-micro-second voltage scaling in SoCs has pushed regulators to be fully integrated in-package and/or on-chip. Buck converters still offer the highest efficiency compared to other converter topologies but present integration challenges that this work addresses by utilizing a package integrated voltage regulator (PIVR) with full back-end integration of magnetic-core power inductors. The on-chip D-LDO demonstrated a fully standard cell-based distributed design integrated into an advanced 12nm FinFET process. A focus on reducing excess timing margins has led to a push towards advanced clocking mechanisms like adaptive clocking, which has caused a shift from more traditional PLL-based dynamic voltage and frequency scaling to unified voltage and frequency scaling architectures that use tunable replica oscillators to decrease timing excess timing margins due to voltage droop, process variations, thermals, and aging. This work implemented UVFS with an HVR architecture using a multi-output PIVR cascaded with on-chip D-LDOs and demonstrated it in a complex 22-core network-on-chip SoC in 12nm FinFET.

Networks-on-Chip (NoC) have been proposed to meet many challenges of modern Systems-on-Chip (SoC) design and manufacturing. At the architectural level, a clean separation of computation and communication helps integration and verification. Networking abstraction of the communication infrastructure also promotes reuse and fast development. But the benefit is most visible when it comes to circuit and physical design. Networks can be made sparse and regular and thus facilitate placement and route. It is also much easier to reach timing and power closure as NoC shield communication details away from complicating analysis. Last but not the least, networks are flexible at the design stage and adaptable post-silicon. Many techniques of tackling process variation and interconnect failure can be built upon NoC. However, when interconnects are time multiplexed in a NoC, the network’s performance will deteriorate if it is not scheduled properly. For a wide range of applications, the traffic on the network can be determined before run-time and offline scheduling offers guaranteed performance and enables simple design. We propose a synthesis flow that takes the data flow graph of the application and a network topology as inputs; and outputs an offline schedule that can be deployed directly to the NoC. We analyze the complexity of combinatorial problems that arise from this context and provide efficient heuristics when polynomial time algorithms are not available assuming P [not equal to] NP. Results on LDPC decoding and FFT designs are compared with previous ones. We further apply our findings to parallel shared memories (PSM) and formalize the PSM architecture and its scheduling problem. An efficient heuristic is derived from our algorithm for unbuffered networks. Another application exemplifies how the NoC can be reprogrammed after silicon is back from fab in order to avoid failed interconnects due to process variation. A simple statistical model is studied and the simulation result is rather interesting. We find out that high performance and yield are not always at conflict if we are able to change the network schedule based on silicon diagnosis. / text

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-07-06T13:04:33Z No. of bitstreams: 1 WILLIAM SCHNEIDER_DIS.pdf: 3430246 bytes, checksum: 5fc61ba11d1155b509058a5d6a0c34b9 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-07-10T14:27:37Z (GMT) No. of bitstreams: 1 WILLIAM SCHNEIDER_DIS.pdf: 3430246 bytes, checksum: 5fc61ba11d1155b509058a5d6a0c34b9 (MD5) / Made available in DSpace on 2018-07-10T14:37:58Z (GMT). No. of bitstreams: 1 WILLIAM SCHNEIDER_DIS.pdf: 3430246 bytes, checksum: 5fc61ba11d1155b509058a5d6a0c34b9 (MD5) Previous issue date: 2014-03-13 / The increase in the number of cores available in Systems on a Chip has enabled the design of circuits with increasingly aggressive specifications. Efficient interconnection architectures such as intrachip networks are critical to the viability of these projects. However, measuring and comparing performanceof these networks for a given system is still a challenging task, which results from: (i) the complexity imposed by the abundance of available options in the design space of these networks; (ii) the current non-adoption of a unique evaluation platform to compare different networks proposals; (iii) the fact that the network traffic has a greater influence on the performance of such networks than any other design characteristic. This work has as main strategic goal the evaluation and comparison of different intrachip network architectures through the use of a unified evaluation platform. It adopts Nocbench, a recent platform, already validated in some contexts and proposed as a standard for the evaluation of intrachip networks. The employed evaluation method is based on the simulation of networks and uses as input traffic and computation models described in the form of traces, both extracted from real application. The main contributions of this work reside in: (i) the proposal of several enhancements to the chosen platform; (ii) the development of modules added to integrate the networks Hermes HS,Hermes OO, Hermes TB, Hermes VC, and YeaH from the author?s research group to the platform; (iii) the enhancement of the platform performance evaluation process, through the inclusion of metrics usually employed to compare intrachip networks, including: latency, throughput and jitter. A set of experiments validates the contributions and demonstrate the use the Nocbench platform as a useful tool in the comparison of intrachip networks of diverse origins. / O aumento no n?mero de n?cleos presentes em Sistemas Integrados em Chip tem proporcionado o projeto de circuitos com especifica??es cada vez mais agressivas. Arquiteturas de interconex?o eficientes tais como as redes intrachip s?o fundamentais para a viabilidade destes projetos. Entretanto, medir e comparar o desempenho destas redesainda ? uma tarefa desafiadora, resultado: (i) da complexidade imposta pela abund?ncia de op??es dispon?veis no espa?o de projeto destas redes; (ii) da atual n?o ado??o de uma mesma plataforma de avalia??o para a compara??o de diferentes propostas de redes; (iii) e do fato de o tr?fego de rede exercer uma influ?ncia muito maior do que qualquer caracter?stica de projeto no desempenho destas. Este trabalho tem como principal objetivo estrat?gico a avalia??o e compara??o de diferentes arquiteturas de redes intrachip atrav?s de uma plataforma de avalia??o unificada. Adota-se Nocbench, uma plataforma recente, j? validada em alguns contextos e proposta como um padr?o para a avalia??o de redes intrachip. O m?todo de avalia??o empregado baseia-se na simula??o de redes e utiliza como entrada modelos de tr?fego e de computa??o descritos sob a forma de traces, ambos extra?dos de aplica??es reais. As principais contribui??es do trabalho residem: (i) na proposta de diversas melhorias para a plataforma escolhida; (ii) no desenvolvimento de m?dulos para a integra??o das redes Hermes HS, Hermes OO, Hermes TB, Hermes VC e YeaHdo grupo de pesquisa do Autor ? plataforma em quest?o; (iii) no aprimoramento do processo de avalia??o de desempenho da plataforma, atrav?s da inclus?o de m?tricas comumente utilizadas para comparar redes intrachip, incluindo: lat?ncia, vaz?oe jitter. Um conjunto de experimentos valida as contribui??es e demonstra o uso da plataforma Nocbench como uma ferramenta ?til na compara??o de redes intrachip de origens diversas.

Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.

<p>Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.</p>

<p>During the past years has the Nostrum Network on Chip <i>(NoC)</i> been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties <i>(IP) </i>on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.</p><p>Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.</p><p>Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce</p><p>the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called<i> Data Motorways</i> achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in</p><p>hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.</p><p>This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways</p><p>can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.</p>