Silver sintering technology has received considerable attention in recent years because it has the potential to be a suitable interconnection material for high-temperature power electronic packaging, such as high melting temperature, high electrical/thermal conductivity, and excellent mechanical reliability. It should be noted, however, that pressure (usually between three to five MPa) was added during the sintering stage for attaching power chips with area larger than 100 mm2. This extra pressure increased the complexity of the sintering process. The maximum chip size processed by pressure-free sintering, in the published resources, was 6 x 6 mm2. One objective of this work was to achieve chip-attachment with area of 13.5 x 13.5 mm2 (a chip size of one kind of commercial IGBT) by pressure-free sintering of nano-silver paste. Another objective was to fabricate high-power (1200 V and 150 A) multi-chip module by pressure-free sintering. In each module (half-bridge), two IGBT dies (13.5 x 13.5 mm2) and two diode dies (10 x 10 mm2) were attached to a DBC substrate. Modules with solder joints (SN100C) and pressure-sintered silver joints were also fabricated as the control group. The peak temperature in the process of of pressure-free sintering of silver was around 260oC, whereas 270oC for vacuum reflowing of solder, and 280oC under three MPa for pressure-sintering of silver. The process for wire bonding, lead-frame attachment, and thermocouple attachment are also recorded. Modules with the above three kinds of joints were first characterized by electrical methods. All of them could block 1200 V DC voltage after packaging, which is the voltage rating of bare dies. Modules were also tested up to the rated current (150 A) and half of the rated voltage (600 V), which were the test conditions in the datasheet for commercial modules with the same voltage and current ratings. I-V characteristics of packaged devices were similar (on-resistance less than 0.5 mohm). All switching waveforms at transient stage (both turn-on and turn-off) were clean. Six switching parameters (turn-on delay, rise time, turn-off delay, fall time, turn-on loss, and turn-off loss) were measured, which were also similar (<9%) among different kinds of modules. The results from electrical characterizations showed that both static characterizations and double-pulse test cannot be used for evaluating the differences among chip-attach layers. All modules were also characterized by their thermal performances. Transient thermal impedances were measured by gate-emitter signals. Two setups for thermal impedance measurement were used. In one setup, the bottoms of modules were left in the air, and in the other setup, bottoms of modules were attached to a chiller (liquid cooling and temperature controlled at 25oC) with thermal grease. Thermal impedances of three kinds of modules still increased after 40 seconds for the testing without chiller, since the thermal resistance of heat convection from bottom copper to the air was included , which was much larger than the sum of the previous layers (from IGBT junction, through the chip-attach layer, to the bottom of DBC substrate). In contrast, thermal impedances became almost stable (less than 3%) after 15 seconds for all modules when the chiller was used. Among these three kinds of modules, the module with pressure sintered joints had the lowest thermal impedance and the thermal resistance (tested with the chiller) around 0.609oK/W, In contrast, the thermal resistance was around 964oK /W for the soldered module, and 2.30oK /W for pressure-free sintered module. In summary, pressure-free large-area sintered joints were achieved and passed the fabrication process for IGBT half-bridge module with wiring bonding. Packaged devices with these kinds of joints were verified with good electrical performance. However, thermal performances of pressure-free joints were worse than solder joints and pressure-sintered joints. / Master of Science

Using a novel, adipose-liver, two-organ, human-on-a-chip system, the metabolic disease non-alcoholic fatty liver disease was modeled. This model was then used to test the effects of the gut microbiome on NAFLD progression. Two products of the gut microbiome, Trimethylamine-n-oxide and butyrate, were selected as representatives of potentially harmful and potentially beneficial compounds. A dose response, adipocyte and hepatocyte monocultures controls, and HoaC systems were run for 14 days. Through this experimentation, it was found that a dysbiosis of the gut microbiome could be influencing NAFLD progression. Additionally, further development and discovery regarding adipose-liver systems was added to the ongoing conversation of HoaC systems and their usages.

No description available.

No description available.

No description available.

No description available.

No description available.

As time progresses, computer architects continue to create faster and more complex microprocessors using techniques such as out-of-order execution, branch prediction, dynamic scheduling, and predication. While these techniques enable greater performance, they also increase the complexity and silicon area of the design. This creates larger development and testing times. The shrinking feature sizes associated with newer technology increase wire resistance and signal propagation delays, further complicating large designs. One potential solution is the Single-Chip Message-Passing (SCMP) Parallel Computer, developed at Virginia Tech. SCMP makes use of an architecture where a number of simple processors are tiled across a single chip and connected by a fast interconnection network. The system is designed to take advantage of thread-level parallelism and to keep wire traces short in preparation for even smaller integrated circuit feature sizes. This thesis presents the implementation of the MPI (Message-Passing Interface) communications library on top of SCMP's hardware communication support. Emphasis is placed on the specific needs of this system with regards to MPI. For example, MPI is designed to operate between heterogeneous systems; however, in the SCMP environment such support is unnecessary and wastes resources. The SCMP network is also designed such that messages can be sent with very low latency, but with cooperative multitasking it is difficult to assure a timely response to messages. Finally, the low-level network primitives have no support for send operations that occur before the receiver is prepared and that functionality is necessary for MPI support. / Master of Science

Computer architects continue to push the limits of modern microprocessors. By using techniques such as out-of-order execution, branch prediction, and dynamic scheduling, designers have found ways to speed execution. However, growing architectural complexity has led to unsustained development and testing times. Shrinking feature sizes are causing increased wire resistances and signal propagation, thereby limiting a design's scalability. Indeed, the method of exploiting instruction-level parallelism (ILP) within applications is reaching a point of diminishing returns. One approach to the aforementioned challenges is the Single-Chip Message-Passing (SCMP) Parallel Computer, developed at Virginia Tech. SCMP is a unique, tiled architecture aimed at thread-level parallelism (TLP). Identical cores are replicated across the chip, and global wire traces have been eliminated. The nodes are connected via a 2-D grid network and each contains a local memory bank. This thesis presents the design and analysis of three high-performance applications for SCMP. The results show that the architecture proves itself as a formidable opponent to several current systems. / Master of Science

Los diseños multi-núcleo se están convirtiendo en la solución más popular a la mayoría de las limitaciones de los diseños mono-núcleo. Un diseño multi-núcleo sigue el paradigma de diseño conocido como Sistema dentro del Chip (o SoC , del inglés System on-Chip), en el cuál varios núcleos se integran en un mismo chip. Las prestaciones de un diseño SoC dependen en gran medida de la infraestructura de interconexión que implemente. En este contexto, el paradigma de diseño conocido como red dentro del chip (o NoC, del inglés Network on-Chip) surge como una solución a los desafíos de interconexión presentes en los nuevos diseños de tipo SoC. Para un diseño concreto, el alto número de posibles soluciones basadas en NoCs incrementa la complejidad de analizar el espacio de diseño y de elegir la NoC óptima. La solución más común a este problema pasa por la utilización de herramientas de alto nivel para la obtención de estimaciones sobre las prestaciones de cada posible solución, que posteriormente serán utilizadas por el diseñador para cribar el espacio de diseño en las primeras etapas del proceso de diseño. Pero hay una gran diferencia entre las prestaciones estimadas por herramientas de alto nivel y las prestaciones reales obtenidas una vez el sistema se implementa. Este trabajo se centra en el desarrollo de nuevas herramientas de alto nivel de diseño, modelado y simulación de NoCs, con el fin de cribar el espacio de diseño de los candidatos menos atractivos. En un primer paso, nos centraremos en el diseño y desarrollo de una plataforma experimental para analizar arquitecturas alternativas para el diseño de NoCs de forma que permitan evaluar cualquier punto del espacio de diseño de forma rápida y precisa, mediante la anotación de algunos parámetros claves del proceso de síntesis física. En el segundo paso, se revisaron arquitecturas y técnicas de diseño adoptadas del dominio de las redes de interconexión fuera del chip, seleccionando las más prometedoras y, en algunos casos, explotando las características propias de las redes dentro de chip para obtener nuevas soluciones. Este paso, preliminar al desarrollo de la herramienta para la realización de exploraciones del espacio de diseño (o herramientas DSE, del inglés Design Space Exploration), tiene como objetivo depurar las técnicas para la abstracción de los efectos de la implementación física de las NoCs sobre sus prestaciones. / Gilabert Villamón, F. (2011). Design Space Exploration for Networks On-chip [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/11521