No description available.

For the on-chip bus, flexibility is the key to reuse by enabling developers to select the optimal architecture to efficiently meet the performance requirements of a wide variety of systems. AMBA is an open standard, on-chip bus specification that details a strategy for the interconnection and management of functional blocks that makes up a System-on-Chip (SoC). AMBA will let designers multiply the total bandwidth available in a system without changing the bus interface on existing intellectual property (IP) cores. Sometimes, the SoC designer to select the optimal combination of bus frequency (to match the peripherals) and number of channels (to achieve the bandwidth), using the AMBA Multi-layer architecture. The AHB of the AMBA System Bus connects embedded processors such as an ARM core to high-performance peripherals, DMA controllers, on-chip memory and interfaces. It is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance. In this thesis, we implement an software, Automatic Generation of On-Chip Bus Infrastructure for SoC, and it supports the AMBA AHB, Multi-layer AHB architecture to optimize system bandwidth, or AHB-Lite to streamline single master layers. By user set up, it can generate the relative on-chip bus infrastructure. We use each AHB Monitor of SDV and Synposys to validate the protocol of infrastructure respectively. In Test Patterns, we use Bus Functional Model to verify all type transfers of bus. In hardware implement, we use SYS32TM, SYS32TME, SYS16TM, and MEMCU to integrate three type AHBs. Every example, we also build FPGA prototyping and chip layout. We do this to validate our on-chip bus infrastructure.

Network-on-Chip (NoC) is communication infrastructure for future multi-core Systems-on-Chip (SoCs). NoCs are expected to overcome scalability and performance limitations of Point-to-Point (P2P) and bus-based communication systems. The routing algorithm of a given NoC affects the performance of the system measured with respect to metrics such as latency, throughput and load distribution. In this thesis, the popular Orthogonal One Turn (O1TURN) and Dimension Order Routing algorithms (DOR) for 2D-meshes are implemented by computer simulation. Investigating the effect of parameters such as packet, buffer and topology sizes on the performance of the network, it is observed that the center of the network is loaded more than the edges. A new routing algorithm is proposed and evaluated to achieve a more balanced load distribution. The results show that this goal is achieved with a trade off in latency and throughput in DOR and O1TURN.

This dissertation aims to evaluate the package effects on the performance of radio frequency integrated circuits (RFICs) for wireless applications. A model-based study is presented to compare the effects between flip-chip and wire-bond packages on a front-end cascode low-noise amplifier (LNA) in a 2.45 GHz CMOS wireless local area network (WLAN) receiver. To construct the package electrical models, specific modeling dies are designed to help extract the equivalent-circuit elements from measured S-parameters for chip-package interconnects. Furthermore, the ground-proximity effect on on-chip spiral inductors in a flip-chip package is first observed and presented in this modeling study. Excellent agreement between modeling and measurement is obtained by up to 20 GHz for a 64-pin flip-chip ball grid array (FC-BGA) package and a 64-pin wire-bond quad flat nonlead (WB-QFN) package. For practical applications, the established package models are used to predict the degradation of the figure of merit for the cascode LNA under packaged condition. Chip-package co-simulations can achieve good agreement with measurements, and thus can persuasively account for the complete effects caused by the two different packages on the cascode LNA. To simultaneously consider the package and board interconnect effects on RFICs, this dissertation also designs and implements a 1.95 GHz upconverter for the wideband code-division multiple-access (W-CDMA) transmitter. Specific ground wire-bonding and board connection are designed to minimize the linearity degradation due to package and board interconnects. Nonlinear analysis technique is also used to evaluate the nonlinear distortion of the upconverter in the chip-package-board co-design phase. The final measurement results have successfully verified the co-design predictions and simulations for this upconverter.

Avatrel 8000P's excellent photo-definition properties and mechanical strength make it an ideal polymer collar material. Avatrel 8000P is a high contrast, I-line sensitive mixture that can be developed in traditional aqueous-base developers. The great photolithographical performance of this photopolymer can be partly contributed to the minimal amount of light absorbed by the base norbornene polymer. The processing conditions noted in this work are an optimized version, which have been shown to give superior photolithographical performance. The simple baking procedures make Avatrel 8000P easier to process than SU-8. The ability to develop Avatrel 8000P in aqueous base can reduce chemical waste. As shown by SEM images, high fidelity structures with aspect ratios of 7:1 can be fabricated in thick films with vertical sidewalls. Bonding between two copper surfaces over various gap sizes was achieved by electroless deposition without the addition of surfactants or inhibitors in the bath. The effect of anneal temperature on the electroless bond formed was analyzed. The electroless bond strength increased with anneal temperature. However, the bond strength estimation for samples annealed at 80°C to 120°C is a minimum value due to the failure location of most of the pillars and the resulting area used in the calculation of bond strength. Grain growth from copper recrystallization and removal of small defects improve the bond strength. Large voids at the interface of the two pillars were related to rough starting surfaces for the electroplated pillars.

Low-loss off-chip interconnects are required for energy-efficient communication in dense microprocessors. To meet these needs, air cavity parallel plate and microstrip lines with copper conductors were fabricated on an FR-4 epoxy-fiberglass substrate using conventional microelectronics manufacturing techniques. Copper transmission lines were separated by a composite dielectric of air and Avatrel 2000P and by a dielectric layer of air only. The composite dielectric lines were characterized to 10 GHz while the all air dielectric lines were characterized to 40 GHz. The transmission line structures showed loss as low 1.5 dB/cm at 40 GHz with an effective dielectric constant below 1.4. These novel structures show low loss in the dielectric due to the reduced relative permittivity and loss tangent introduced by the air cavity. Transmission line structures with a composite dielectric were built by coating the sacrificial polymer poly(propylene carbonate) (PPC) over a copper signal line, encapsulating with an overcoat polymer, electroplating a ground line, and decomposing PPC to form an air cavity. The signal and ground wires were separated by a layer of 15 µm of air and 20 µm of Avatrel 2000P. Air cavity formation reduced dielectric constant more than 30 percent and loss of less than 0.5 dB/cm was measured at 10 GHz. Residue from PPC decomposition was observed in the cavity of composite dielectric structures and the decomposition characteristics of PPC were evaluated to characterize the residue and understand its formation. Analysis of PPC decomposition based on molecular weight, molecular backbone structure, photoacid concentration and vapor pressure, casting solvent, and decomposition environment was performed using thermogravimetric analysis and extracting kinetic parameters. Novel interaction of copper and PPC was observed and characterized for the self-patterning of PPC on copper. Copper is dissolved from the surface during PPC spincoating and interacts with the polymer chains to improve stability. The improved thermal stability allows selective patterning of PPC on copper. Decomposition characteristics, residual metals analysis, and diffusion profile were analyzed. The unique interaction could simplify air-gap processing for transmission lines. Inorganic-organic hybrid polymers were characterized for use as overcoat materials. Curing characteristics of the monomers and mechanical properties of the polymer films were analyzed and compared with commercially available overcoat materials. The modulus and hardness of these polymers was too low for use as an air-gap overcoat, but may be valuable as a barrier layer for some applications. The knowledge gained from building transmission line structures with a composite dielectric, analyzing PPC decomposition, interaction with copper, and comparison of hybrid polymers with commercial overcoats was used to build air-gap structures with improved electrical design. The ground metal was separated from the signal only by air. The signal wire was supported from above using 60 µm of Avatrel 8000P as an overcoat. Structures showed loss of less than 1.5 dB/cm at 40 GHz, the lowest reported value for a fully encapsulated transmission line structure.

No description available.

Das als Trace bezeichnete nicht-invasive Aufzeichnen von Systemzuständen, während ein eingebettetes System unter realen Einsatzbedingungen in Echtzeit läuft und mit der Systemumgebung interagiert, ist ein wichtiger Teil von Softwaretests. Die Notwendigkeit für den On-Chip-Trace resultiert aus der rückläufigen Einsetzbarkeit etablierter Werkzeuge für den Off-Chip-Trace. Ein wesentlicher Bestandteil von On-Chip-Trace-Architekturen ist die Volumenreduktion der Tracedaten in deren Entstehungsgeschwindigkeit direkt auf dem Chip. Der Schwerpunkt liegt auf dem Trace des Instruktionsflusses von Prozessoren. Der aktuelle Stand der Forschung zeigt zwei Ausprägungen. Bei einfachen Lösungen ist der Kompressionsfaktor zu klein. Aufwendigere Lösungen liefern einen unvollständigen Instruktionstrace, wenn auch sequentielle Befehle bedingt ausgeführt werden. Bisher existieren keine Lösungen, die einen vollständigen Instruktionstrace mit hoher Kompression realisieren. Diese Lücke wird in der vorliegenden Arbeit geschlossen. Der systematische Entwurf der neuen On-Chip-Trace-Architektur beginnt mit der umfassenden Analyse typischer Benchmarkprogramme. Aus den Ergebnissen werden grundlegende Entwurfsentscheidungen abgeleitet. Diese Bitsequenzen von Ausführungsbits, die bei der bedingten Befehlsausführung entstehen, und die Zieladressen ausgeführter indirekter Sprünge werden in unabhängigen Kompressoren verarbeitet. Ein nachgeschalteter Kompressor für die Messages der anderen beiden Kompressoren ist optional und kann die Kompression weiter steigern. Diese Aufteilung stellt ein architektonisches Novum dar. Die Kompression von Bitsequenzen ist bisher ein weitestgehend unbehandeltes Feld. Implementiert worden ist hierfür ein gleitendes Wörterbuch mit der Granularität von Einzelbits. Die Vergleiche mit den untersuchten existierenden Architekturen zeigen die Überlegenheit der neuen Architektur bei der Kompression. Ein vollständiger Instruktionstrace ist für Prozessoren mit und ohne bedingt ausführbaren sequentiellen Befehlen realisiert worden.

Nowadays, there is a growing demand for high frequency-bandwidth mm-wave (30-300 GHz) electronic wireless transceiver systems to support applications such as high data-rate wireless communication and high resolution imaging. Such mm-wave systems are becoming more feasible due to the extreme transistor downscaling in silicon-based integrated circuits, which enabled densely-integrated high-speed elec- tronics operating up to more than 100 GHz with low fabrication cost. To further enhance system integrability, it is required to implement all wireless system compo- nents on the chip. Presently, the last major barrier to true System-on-Chip (SoC) realization is the antenna implementation on the silicon chip. Although at mm-wave frequencies the antenna size becomes small enough to fit on chip, the antenna performance is greatly deteriorated due the high conductivity and high relative permittivity of the silicon substrate. The negative e↵ects of the silicon substrate could be avoided by using a metallic reflecting surface on top of silicon, which e↵ectively isolates the antenna from the silicon. However, this approach has the shortcoming of having to implement the antenna on the usually very thin silicon oxide layer of a typical CMOS fabrication process (10’s of μm). This forces the antenna to be in a very close proximity (less than one hundredth of a wavelength) to the reflecting surface. In this regime, the use of conventional metallic reflecting surface for silicon shielding has severe e↵ects on the antenna performance as it tends to reduce the antenna radiation resistance resulting in most of the energy being absorbed rather than radiated. In this work, the use of specially patterned reflecting surfaces for improving on- chip antenna performance is investigated. By using a periodic metallic surface on top of a grounded substrate, the structure can mimic the behavior of a perfect mag- netic conductor, hence called Artificial Magnetic Conductor (AMC) surface. Unlike conventional ground plane reflecting surfaces, AMC surfaces generally enhance the radiation and impedance characteristics of close-by antennas. Based on this property, a ring-based AMC reflecting surface has been designed in the oxide layer for on-chip antennas operating at 94 GHz. Furthermore, a folded dipole antenna with its associ- ated planar feeding structures has been optimized and integrated with the developed ring-based AMC surface. The proposed design is then fabricated at KAUST clean- room facilities. Prototype characterization showed very promising results with good correlation to simulations, with the antenna exhibiting an impedance bandwidth of 10% (90-100 GHz) and peak gain of -1.4 dBi, which is the highest gain reported for on-chip antennas at this frequency band without the use of any external o↵-chip components or post-fabrication steps.

Unlike straight turning, the effective cutting conditions and tool geometry in contour turning operations are changing with changing workpiece profile. This causes a wide variation in machining performance such as chip flow and chip breakability during the operation. This thesis presents a new methodology for optimizing the machining performance, namely, chip breakability and surface roughness in contour finish turning operations. First, a computer program to calculate the effective cutting conditions and tool geometry along the contour workpiece profile is developed. Second, a methodology to predict the chip side-flow for complex grooved tool inserts is formulated and integrated in the current predictive model for contour turning operations. Third, experimental databases are established and numerical data interpolation is applied to predict the cutting forces, chip shape and size, and surface roughness for 1045 steel work material. Finally, based on the machining performance predictions, a new optimization program is developed to determine the optimum cutting conditions in contour finish turning operations.