In system-on-chip designs, memory designs store data to be accessed by processing modules. Memory access time can affect overall system performance significantly. In this research, we implemented a configurable architecture of a basic memory module and its design composition, including memory interface, memory controller, memory array, row buffer, row decoder and column decoder. We explore various memory module designs. Utilizing the configurable architecture, we can effectively reduce design time and improve access time of memory module designs. We also realized these functionalities in SystemC language and performed configurability experiments.

We propose a synthesis methodology for Network-on-Chips (NoC) or NoC-based multiprocessor systems-on-chip (MPSoCs) for application-specific or irregular topology generation.We first propose simultaneously synthesize both for processor and communication architectures in order to estimate area and routing more accurately during floorplanning stage, which is different with traditional router and link insertion after floorplanning. Our NoC topology generation is simultaneously optimized for fast, low power and wirelength. Compared with the state of art, our results outperforms averagely 445.45 X in CPU time, 33.20 % in power consumption, and 96.86 % in wirelength at cost of NoC Size of more 2.26 % because our method considering router shape; the number of routers of more 20.63 % because our method only allows router port limit of 5; the number of links of more 3.93 % because our method allows different link lengths. Also our method is scalable and experiments of 2 X, 4 X, 8 X and 16 X outperform averagely 355,089.11 X in CPU time, 1.21 X in the number hops, 78.33 % in power consumption. Our experimental results show our synthesis method is effective, efficiently and scalable.

Zugl.: Wien, Techn. Univ., Diss., 2009

Thesis (M.S.)--Mechanical Engineering, Georgia Institute of Technology, 2004. / Daniel Baldwin, Committee Chair; Suresh Sitaraman, Committee Member; Steven Danyluk, Committee Member. Includes bibliographical references (leaves 238-241).

Thesis (Ph. D.)--School of Materials Science and Engineering, Georgia Institute of Technology, 2004. Directed by C.P. Wong. / Includes bibliographical references (leaves 275-289).

Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Baldwin, Daniel; Committee Member: Colton, Jonathan; Committee Member: Ghiaasiaan, Mostafa; Committee Member: Moon, Jack; Committee Member: Tummala, Rao. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Software plays an important role in making products usable. We couldn’t imagine a laptop without software that run it making the things it does possible with the laptop hardware. Software has penetrated into several industries making significant contribution in how the products are designed and to make them more usable. This thesis focuses on semiconductor industry and analyzes the role played by software to enhance their products and differentiate them from competition. In this context, the thesis looks at acquisition of software companies by chip companies and analyzes them to determine the benefits and how it changed the market space. In a semiconductor company, the focus is predominantly on hardware. Although software is equally crucial to the success of the product, not much focus is placed on it in terms of innovation and building sustained software IP portfolio. One of the questions that this thesis tries to answer is how to build a robust software IP portfolio in a chip company. Case studies of different products were conducted to analyze their IP building strategies in general and focusing specifically on software patenting in terms number of patents filed and procedures adopted to encourage it. It looks closely at the best and not-so-best practices adopted by the teams and analyzing them to determine why certain initiatives succeeded while others failed. A crucial aspect of building software IP pipeline is to involve junior level engineers in this process. The thesis looks at some of the strategies companies could use to bring the culture of patents to the lowest levels of engineers. Typically the senior engineers are well tuned in to the process and regularly file patents while the junior engineers don’t. This is crucial to the company since today’s junior engineer is tomorrow’s senior engineer leading technology initiatives. The thesis concludes by putting forward recommendations to encourage software patenting. / text

Medulloblastoma (MB) is the most common malignant brain tumor affecting children. The transcription factors MYCN and SOX9 are associated with initiation, maintenance and recurrence of MB and are also connected to more aggressive tumors. In this study, a ChIP was performed to isolate DNA from genes that are transcriptionally regulated by these proteins. Identification of these target genes will reveal new potential drug targets and help us better understand the functions of MYCN and SOX9. The ChIP was not fully optimized during this project and the target genes were not sent for sequencing and identified. To study the connection between SOX9 and recurrence, cells with different levels of SOX9 were treated with drugs, after which cell viability was measured. No significant difference in resistance could be measured. Change in expression level of MYCN, SOX9 and other relevant genes after drug treatment was also studied. The results show an increase in SOX9 and HES1, suggesting that these genes are involved in tumor recurrence.

Not available / text

Electromigration related damage in solder bumps is one of the emerging issues resulting from the fast scaling-down of features in semiconductor packages. Although the electromigration phenomenon has been intensively studied on silicon level interconnect lines since the late 1960s, it is far less understood in solder bumps. Electromigration in solder joints can be quite different from that of the interconnects due to the differences in material systems and structures. This study addressed the solder joint electromigration and contained three major objectives. The first objective of this study was to set up an effective experimental technique to examine the damage development and determine the time-to-failure in the electromigration tests. The structure and dimension of the flip chip solder bump is very different from that of the chip level interconnect. Consequently, the traditional failure tracking method based on 2-point resistance monitoring is no longer able to provide real-time damage evolution information. A test system based on a Wheat stone bridge circuit was introduced. The technique showed the capability of detecting milliohm resistance changes and could track the interfacial crack growth induced by electromigration damage. Other aspects of the experiment, such as temperature and current distribution inside the test structure, were also examined so that proper lifetime could be extrapolated from testing condition to normal working condition. The second objective was to examine the failure mechanisms in solder bump electromigration which could be significantly different between various solder bump systems. Pb-free and high-Pb solder alloys with different UBM configurations were studied. The research results showed that the most active region during solder bump electromigration was the under bump metallization (UBM) layer and its interface with the solder due to the intermetallic compound formation and UBM dissolution. Therefore, the electromigration-induced damage occurred mostly in this region. The failure mechanisms were found to be highly dependent on the material system as well as the temperature. The third objective was to determine the statistical lifetime of the flip chip solder bumps under electromigration. Lognormal distributions were used to fit the lifetime. The temperature and current dependence was assumed to follow Black's equation and the activation energies was calculated from that. The results showed that the traditional Black's equation might not be applicable to solder bump electromigration due to the different failure mechanism at different temperatures. Special attention is needed to set up design rules for maximum operating current and temperature for a solder bump structure when extrapolating data from high temperature. / text