This text describes different aspects of the design of a Doctor-on-a-Chip device. Doctor-on-a-Chip is a DNA analysis system integrated on a single chip, which should provide all of the advantages that stem from the system integration, such as small sample volume, fast and accurate analysis, and low cost. The text describes all of the steps of the on-chip sample analysis, including DNA extraction from the sample, purification, PCR amplification, novel dielectrophoretic sorting of the DNA molecules, and finally detection. The overview is given of the technologies which are available to make the integration on a single chip possible. The microfluidic technologies that are used to manipulate the sample and other chemical reagents are already known and in this text they are analyzed in terms of their feasibility in the on-chip system integration. These microfluidic technologies include, but are not limited to, microvalves, micromixers, micropumps, and chambers for PCR amplification. The novelty in the DNA analysis brought by Doctor-on-a-Chip is the way in which the different DNA molecules in the sample (for example, human and virus DNA) are sorted into different populations. This is done by means of dielectrophoresis – the force experienced by dielectric particles (such as DNA molecules) when subject to a non-uniform electric field. Different DNA molecules within a sample experience different dielectrophoretic forces within the same electric field, which makes their separation, and therefore detection, possible. In this text, the emphasis is put on numerical modelling of the dielectrophoretic effect on biological particles. The importance of numerical modelling lies in the fact that with the accurate model it is easier to design systems of microelectrodes for dielectrophoretic separation, and tune their sub-micrometre features to achieve the maximum separation efficacy. The numerical model described in this text is also experimentally verified with the novel microelectrodes design for dielectrophoretic separation, which is successfully used to separate the mixture of different particles in the micron and sub-micron range.

Com o crescimento acelerado da complexidade das aplicações e softwares que exigem alto desempenho, o hardware e sua arquitetura passou por algumas mudanças para que pudesse atender essa necessidade. Uma das abordagens propostas e desenvolvidas para suportar essas aplicações, foi a integração de mais de um core de processamento em um único circuito integrado. Inicialmente, a comunicação utilizando barramento foi escolhida, pela sua vantagem de reuso comparado a ponto a ponto. No entanto, com o aumento acelerado da quantidade de cores nos Systems-on-Chip (SoC), essa abordagem passou a apresentar problemas para suportar a comunicação interna. Uma alternativa que vem sendo explorada é a Network-on-Chip (NoC), uma abordagem que propõe utilizar o conhecimento de redes comuns em projetos de comunicação interna de SoC. Esse trabalho fornece uma arquitetura de NoC completa, configurável, parametrizável e no padrão Ethernet. Os três módulos básicos da NoC, Network Adapter (NA), Link e Switch, são implementados e disponibilizados. Os resultados foram obtidos utilizando o FPGA Stratix IV da Altera. As métricas de desempenho utilizadas para validação da NoC são a área no FPGA e o atraso na comunicação. Os parâmetros disponibilizados são referentes as configurações dos módulos desenvolvidos, considerando características apresentadas de aplicações DSP (Digital Signal Processing). O experimento utilizando dois NAs, dois cores e um Switch precisou de 7310 ALUTs do FPGA EP4SGX230KF40C2ES o que corresponde a 4% dos seus recursos lógicos. O tempo gasto para a transmissão de um quadro ethernet de 64 Bytes foi de 422 ciclos de clock a uma frequência de 50MHz. / With the accelerated growth of the complexity of the software and applications that require high performance, hardware and its architecture has undergone a few changes so it could meet that need. One of the proposals and approaches developed to support these applications, was the integration of more than one core processing in a single integrated circuit. Initially, the bus communication architecture was chosen, using for its reuse benefit compared to point-to-point. However, with the cores number increase in Systems-on-Chip (SoC), this approach began to present problems to support internal communication. An alternative that has been explored is the Network-on-Chip (NoC), an approach that proposes to use knowledge of common networks on internal communication projects of SOC. This dissertation focuses is to provide a complete NoC architecture, configurable, customizable and on standard Ethernet. The three NoC basic modules, Network Adapter (NA), Link and Switch, are implemented. The results were obtained using the Stratix IV FPGA. The performance metrics used for NoC validation are silicon area and latency. The available parameters are related to developed modules settings, considering features presented of DSP applications. The experiment using two NA, two cores and one Switch needed 7310 FPGA ALUTs which corresponds to 4% of their logical resources. The time for the transmission of an ethernet frame of 64 Bytes was 422 clock cycles at 50 MHz.

Due to the tight power budget and reduced time-to-market, Systems-on-Chip (SoC) have emerged as a power-efficient solution that provides the functionality required by target applications in embedded systems. To support a diverse set of applications such as real-time video/audio processing and sensor signal processing, SoCs consist of multiple heterogeneous components, such as software processors, digital signal processors, and application-specific hardware accelerators. These components offer different flexibility, power, and performance values so that SoCs can be designed by mix-and-matching them. With the increased amount of heterogeneous cores, however, the traditional interconnects in an SoC exhibit excessive power dissipation and poor performance scalability. As an alternative, Networks-on-Chip (NoC) have been proposed. NoCs provide modularity at design-time because communications among the cores are isolated from their computations via standard interfaces. NoCs also exploit communication parallelism at run-time because multiple data can be transferred simultaneously. In order to construct an efficient NoC, the communication behaviors of various heterogeneous components in an SoC must be considered with the large amount of NoC design parameters. Therefore, providing an efficient NoC design and optimization framework is critical to reduce the design cycle and address the complexity of future heterogeneous SoCs. This is the thesis of my dissertation. Some existing design automation tools for NoCs support very limited degrees of automation that cannot satisfy the requirements of future heterogeneous SoCs. First, these tools only support a limited number of NoC design parameters. Second, they do not provide an integrated environment for software-hardware co-development. Thus, I propose FINDNOC, an integrated framework for the generation, optimization, and validation of NoCs for future heterogeneous SoCs. The proposed framework supports software-hardware co-development, incremental NoC design-decision model, SystemC-based NoC customization and generation, and fast system protyping with FPGA emulations. Virtual channels (VC) and multiple physical (MP) networks are the two main alternative methods to provide better performance, support quality-of-service, and avoid protocol deadlocks in packet-switched NoC design. To examine the effect of using VCs and MPs with other NoC architectural parameters, I completed a comprehensive comparative analysis that combines an analytical model, synthesis-based designs for both FPGAs and standard-cell libraries, and system-level simulations. Based on the results of this analysis, I developed VENTTI, a design and simulation environment that combines a virtual platform (VP), a NoC synthesis tool, and four NoC models characterized at different abstraction levels. VENTTI facilitates an incremental decision-making process with four NoC abstraction models associated with different NoC parameters. The selected NoC parameters can be validated by running simulations with the corresponding model instantiated in the VP. I augmented this framework to complete FINDNOC by implementing ICON, a NoC generation and customization tool that dynamically combines and customizes synthesizable SystemC components from a predesigned library. Thanks to its flexibility and automatic network interface generation capabilities, ICON can generate a rich variety of NoCs that can be then integrated into any Embedded Scalable Platform (ESP) architectures for fast prototying with FPGA emulations. I designed FINDNOC in a modular way that makes it easy to augmenting it with new capabilities. This, combined with the continuous progress of the ESP design methodology, will provide a seamless SoC integration framework, where the hardware accelerators, software applications, and NoCs can be designed, validated, and integrated simultaneously, in order to reduce the design cycle of future SoC platforms.

The progress which has been made in semiconductor chip production in recent years enables a multitude of cores on a single die. However, due to further decreasing structure sizes, fault tolerance and energy consumption will represent key challenges. Furthermore, an efficient communication infrastructure is indispensable due to the high parallelism at those systems. The predominant communication system at such highly parallel systems is a Network on Chip (NoC). The focus of this thesis is on NoCs which are based on deflection routing. In this context, contributions are made to two domains, fault tolerance and dimensioning of the optimal link width. Both aspects are essential for the application of reliable, energy efficient, and deflection routing based NoCs. It is expected that future semiconductor systems have to cope with high fault probabilities. The inherently given high connectivity of most NoC topologies can be exploited to tolerate the breakdown of links and other components. In this thesis, a fault-tolerant router architecture has been developed, which stands out for the deployed interconnection architecture and the method to overcome complex fault situations. The presented simulation results show, all data packets arrive at their destination, even at high fault probabilities. In contrast to routing table based architectures, the hardware costs of the herein presented architecture are lower and, in particular, independent of the number of components in the network. Besides fault tolerance, hardware costs and energy efficiency are of great importance. The utilized link width has a decisive influence on these aspects. In particular, at deflection routing based NoCs, over- and under-sizing of the link width leads to unnecessary high hardware costs and bad performance, respectively. In the second part of this thesis, the optimal link width at deflection routing based NoCs is investigated. Additionally, a method to reduce the link width is introduced. Simulation and synthesis results show, the herein presented method allows a significant reduction of hardware costs at comparable performance. / Die Fortschritte der letzten Jahre bei der Fertigung von Halbleiterchips ermöglichen eine Vielzahl an Rechenkernen auf einem einzelnen Chip. Die in diesem Zusammenhang immer weiter sinkenden Strukturgrößen führen jedoch dazu, dass Fehlertoleranz und Energieverbrauch zentrale Herausforderungen darstellen werden. Aufgrund der hohen Parallelität in solchen Systemen, ist außerdem eine leistungsfähige Kommunikationsinfrastruktur unabdingbar. Das in diesen hochgradig parallelen Systemen überwiegend eingesetzte System zur Datenübertragung ist ein Netzwerk auf einem Chip (engl. Network on Chip (NoC)). Der Fokus dieser Dissertation liegt auf NoCs, die auf dem Prinzip des sog. Deflection Routing basieren. In diesem Kontext wurden Beiträge zu zwei Bereichen geleistet, der Fehlertoleranz und der Dimensionierung der optimalen Breite von Verbindungen. Beide Aspekte sind für den Einsatz zuverlässiger, energieeffizienter, Deflection Routing basierter NoCs essentiell. Es ist davon auszugehen, dass zukünftige Halbleiter-Systeme mit einer hohen Fehlerwahrscheinlichkeit zurecht kommen müssen. Die hohe Konnektivität, die in den meisten NoC Topologien inhärent gegeben ist, kann ausgenutzt werden, um den Ausfall von Verbindungen und anderen Komponenten zu tolerieren. Im Rahmen dieser Arbeit wurde vor diesem Hintergrund eine fehlertolerante Router-Architektur entwickelt, die sich durch das eingesetzte Verbindungsnetzwerk und das Verfahren zur Überwindung komplexer Fehlersituationen auszeichnet. Die präsentierten Simulations-Ergebnisse zeigen, dass selbst bei sehr hohen Fehlerwahrscheinlichkeiten alle Datenpakete ihr Ziel erreichen. Im Vergleich zu Router-Architekturen die auf Routing-Tabellen basieren, sind die Hardware-Kosten der hier vorgestellten Router-Architektur gering und insbesondere unabhängig von der Anzahl an Komponenten im Netzwerk, was den Einsatz in sehr großen Netzen ermöglicht. Neben der Fehlertoleranz sind die Hardware-Kosten sowie die Energieeffizienz von NoCs von großer Bedeutung. Einen entscheidenden Einfluss auf diese Aspekte hat die verwendete Breite der Verbindungen des NoCs. Insbesondere bei Deflection Routing basierten NoCs führt eine Über- bzw. Unterdimensionierung der Breite der Verbindungen zu unnötig hohen Hardware-Kosten bzw. schlechter Performanz. Im zweiten Teil dieser Arbeit wird die optimale Breite der Verbindungen eines Deflection Routing basierten NoCs untersucht. Außerdem wird ein Verfahren zur Reduzierung der Breite dieser Verbindungen vorgestellt. Simulations- und Synthese-Ergebnisse zeigen, dass dieses Verfahren eine erhebliche Reduzierung der Hardware-Kosten bei ähnlicher Performanz ermöglicht.

<p>Transcriptional regulation largely determines which proteins and the protein levels that are found in a cell, and this is crucial in development, differentiation and responses to environmental stimuli. The major effectors of transcriptional regulation are a group of proteins known as transcription factors, which importance is supported by their frequent involvement in mendelian and complex diseases.</p><p>In paper I, we attempted to establish the importance of DNA sequence variation in transcriptional control, by analyzing the potential functionality of polymorphic short repetitive elements as cis-regulatory elements. However, the relevance of this study was constrained by the limited number of analyzed sequences and the <i>in vitro</i> nature of the experiments. To overcome these limitations, (paper II) we optimized an <i>in vivo</i> large-scale technology named ChIP-chip, which couples chromatin immunoprecipitation and microarray hybridization. We successfully identified the binding profiles of metabolic-disease associated transcription factors in 1% of the human genome, using a liver cellular model, and inferred the binding sites at base pair resolution.</p><p>Another important characteristic of transcriptional regulation is its plasticity, which allows adjusting the cellular transcriptome to cellular and environmental stimuli. In paper III, we investigated such plasticity by treating HepG2 cells with butyrate, a histone deacetylase inhibitor (HDACi) and interrogating the changes in histone H3 and H4 acetylation levels in 1% of the genome. Observation of frequent deacetylation around transcription start sites and hyperacetylation at the nuclear periphery challenges pre-assumed HDACi mechanisms of action.</p><p>Finally, in paper IV we extended the DNA binding profiles of the medically relevant transcription factors, USF1 and USF2, and H3 acetylation to the whole non-repetitive fraction of the human genome. Using motif finding tools and chromatin profiling, we uncovered the major determinants of USF-DNA interactions. Furthermore, USFs and H3ac were clearly localized around transcription start sites, frequently in the context of bidirectional promoters.</p>

In the System-on-Chip (SoC) era, common industry estimates are that functional verification takes approximately 70% of the total effort on a project. For the time-to-market constrain, it¡¦s a challenge to reduce the SoC verification/debugging time efficiently. In an SoC, a microprocessor is an essential part of it. First, we focus the debugging problem on microprocessors. An in-circuit emulation (ICE) module that can be embedded with a microprocessor core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typical debugging and testing mechanisms, including boundary scan paths, partial scan paths, single stepping, internal resource monitoring and modification, breakpoint detection, and mode switching between debugging and normal modes. The architecture of the ICE module is parameterized and retargetable to different microprocessors. It has been successfully integrated with two microprocessors with significantly different architectures: one 8-bit industrial embedded microcontroller HT48x00 and one 32-bit ARM7-like embedded microprocessor. FPGA prototypes and chip implementation have been accomplished. Experiments show that real-time (on-line) debugging at full speed is possible with the embedded ICE at a minor gate count overhead. Collecting the program execution traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real time program traces are so huge such that real-time program tracing is often infeasible without proper hardware support. This paper presents a hardware approach to compress program execution traces in real time in order to reduce the trace size. The approach consists of three modularized phases: (1) branch/target filtering, (2) branch/target address encoding and (3) Lempel-Ziv-based data compression. A synthesizable RTL code for the proposed hardware is constructed to analyze the hardware cost and speed and typical multimedia benchmarks are used to measure the compression results. The results show that our hardware is capable of real time compression and achieving compression ratio of 454:1, far better than 5:1 achieved by typical existing hardware approaches. Furthermore, our modularized approach makes it possible to trade off between the hardware cost (typically from 1K to 50K gates) and the achievable compression ratio (typically from 5:1 to 454:1). For SoC debugging, bus signal tracing represents that the information which is generated from the system can be collected for later observation, debugging and analysis. However, the generation rate and the size of real time system traces are so huge such that a mechanism for system tracing that can reduce trace size efficiently is needed. In this paper, we propose a multi-resolution bus trace approach. The hardware bus tracer consists of two major stages: (1) signal monitor & tracing stage, and (2) trace compression stage. In the first stage, designer can trace the signals in detail or in rough depends on the debug purpose. In other word, the multi-resolution trace approach provides the trade-off between trace accuracy and trace depth. In the second stage, the bus tracer compresses the trace size efficiently; therefore the capability of on-chip storage is increased. In the host, the analyzer tool decompresses the trace data for future observation and debugging.

Transcriptional regulation largely determines which proteins and the protein levels that are found in a cell, and this is crucial in development, differentiation and responses to environmental stimuli. The major effectors of transcriptional regulation are a group of proteins known as transcription factors, which importance is supported by their frequent involvement in mendelian and complex diseases. In paper I, we attempted to establish the importance of DNA sequence variation in transcriptional control, by analyzing the potential functionality of polymorphic short repetitive elements as cis-regulatory elements. However, the relevance of this study was constrained by the limited number of analyzed sequences and the in vitro nature of the experiments. To overcome these limitations, (paper II) we optimized an in vivo large-scale technology named ChIP-chip, which couples chromatin immunoprecipitation and microarray hybridization. We successfully identified the binding profiles of metabolic-disease associated transcription factors in 1% of the human genome, using a liver cellular model, and inferred the binding sites at base pair resolution. Another important characteristic of transcriptional regulation is its plasticity, which allows adjusting the cellular transcriptome to cellular and environmental stimuli. In paper III, we investigated such plasticity by treating HepG2 cells with butyrate, a histone deacetylase inhibitor (HDACi) and interrogating the changes in histone H3 and H4 acetylation levels in 1% of the genome. Observation of frequent deacetylation around transcription start sites and hyperacetylation at the nuclear periphery challenges pre-assumed HDACi mechanisms of action. Finally, in paper IV we extended the DNA binding profiles of the medically relevant transcription factors, USF1 and USF2, and H3 acetylation to the whole non-repetitive fraction of the human genome. Using motif finding tools and chromatin profiling, we uncovered the major determinants of USF-DNA interactions. Furthermore, USFs and H3ac were clearly localized around transcription start sites, frequently in the context of bidirectional promoters.

Novel micro patterning techniques have been developed for the patterning of volatile functional materials which cannot be conducted by conventional photolithography. First, in order to create micro patterns of volatile materials (such as bio-molecules and organic materials), micro-contact printing and shadow mask methods are investigated. A novel micro-contact printing technique was developed to generate micro patterns of volatile materials with variable size and density. A PDMS (Polydimethylsiloxane) stamp with 2-dimensional pyramidal tip arrays has been fabricated by anisotropic silicon etching and PDMS molding. The variable size of patterns was achieved by different external pressures on the PDMS stamp. A novel inking process was developed to enhance the uniformity and repeatability in micro-contact printing. The variable density of patterns could be obtained by alignment using x-y transitional stage and multiple stamping with a z-directional moving part. Second, for direct patterning of small molecule organic materials (e.g. pentacene), a novel shadow mask method has been developed with a simple and accurate alignment system. To make accurate dimensions of patterning windows, a silicon wafer was used for the shadow mask since a conventional semiconductor process gives a great advantage for accurate and repeatable fabrication processes. A sphere ball alignment system was developed for the accurate alignment between the shadow mask and the silicon substrate. In this alignment system, four matching pyramidal cavities were fabricated on each side of the shadow mask and silicon wafer substrate using an anisotropic silicon bulk etching. By placing four steel spheres in between the matching cavities, the self-alignment system could be demonstrated with 2-3um alignment accuracy in x-y directions. For OTFT (Organic thin film transistor) application, an organic semiconducting layer was directly deposited and patterned on the substrate using the developed shadow mask method. On the other hand, novel embedding techniques were developed for enabling conventional semiconductor processes including photolithography to be applied on the small substrate. The polymer embedding method was developed to provide an extended processing area as well as easy handling of the small substrate. As an application, post CMOS (Complementary metal-oxide-semiconductor) integration of a relatively large microstructure which might be even larger than the substrate was demonstrated on a VCO (Voltage-controlled oscillator) chip. In addition, micro patterning on the optical fiber was demonstrated by using a silicon wafer holder designed to surround and hold the optical fiber. The micro Fresnel lens could be successfully patterned and integrated on the optical fiber end.

Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused on broad topics such as NOC component micro-architecture, fault-tolerant communication, and system memory architecture. Nonetheless, the design of lowlatency, high-bandwidth, low-power and area-efficient NOC is extremely complex due to the conflicting nature of these design objectives. Benchmarks are an indispensable tool in the design process; providing thorough measurement and fair comparison between designs in order to achieve optimal results (i.e performance, cost, quality of service). This research proposes a benchmarking platform called NoCBench for evaluating the performance of Network-on-chip. Although previous research has proposed standard guidelines to develop benchmarks for Network-on-Chip, this work moves forward and proposes a System-C based simulation platform for system-level design exploration. It will provide an initial set of synthetic benchmarks for on-chip network interconnection validation along with an initial set of standardized processing cores, NOC components, and system-wide services. The benchmarks were constructed using synthetic applications described by Task Graphs For Free (TGFF) task graphs extracted from the E3S benchmark suite. Two benchmarks were used for characterization: Consumer and Networking. They are characterized based on throughput and latency. Case studies show how they can be used to evaluate metrics beyond throughput and latency (i.e. traffic distribution). The contribution of this work is two-fold: 1) This study provides a methodology for benchmark creation and characterization using NoCBench that evaluates important metrics in NOC design (i.e. end-to-end packet delay, throughput). 2) The developed full-system simulation platform provides a complete environment for further benchmark characterization on NOC based MpSoC as well as system-level design space exploration.

It is common to test many hypotheses simultaneously in the application of statistics. The probability of making a false discovery grows with the number of statistical tests performed. When all the null hypotheses are true, and the test statistics are indepen- dent and continuous, the error rates from the family wise error rate (FWER)- and the false discovery rate (FDR)-controlling procedures are equal to the nominal level. When some of the null hypotheses are not true, both procedures are conservative. In the first part of this study, we review the background of the problem and propose methods to estimate the number of true null hypotheses. The estimates can be used in FWER- and FDR-controlling procedures with a consequent increase in power. We conduct simulation studies and apply the estimation methods to data sets with bio- logical or clinical significance. In the second part of the study, we propose a mixture model approach for the analysis of ChIP-chip high density oligonucleotide array data to study the interac- tions between proteins and DNA. If we could identify the specific locations where proteins interact with DNA, we could increase our understanding of many important cellular events. Most experiments to date are performed in culture on cell lines, bac- teria, or yeast, and future experiments will include those in developing tissues, organs, or cancer biopsies, and they are critical in understanding the function of genes and proteins. Here we investigate the ChIP-chip data structure and use a beta-mixture model to help identify the binding sites. To determine the appropriate number of components in the mixture model, we suggest the Anderson-Darling testing. Our study indicates that it is a reasonable means of choosing the number of components in a beta-mixture model. The mixture model procedure has broad applications in biology and is illustrated with several data sets from bioinformatics experiments.