VLSI miniaturization has created the need for high-density, low-cost, monolithically-integrated optical interconnects. High output power photodetectors are needed to directly drive load circuitry, which improves the noise performance and dynamic range of optical communications links by eliminating a post amplifier stage. Elimination of the post amplifier also reduces circuit cost and complexity. A new Si-Ge PIN waveguide photodiode with 31GHz bandwidth and 93% quantum efficiency at 1550nm has been developed by Yin et al., which was fabricated using standard CMOS processes on a Silicon substrate. This thesis demonstrates a method for improving the RF power extraction from these photodiodes by increasing the impedance of the load. An RF output power improvement of 5.5dB is obtained by increasing the load resistance from 50 ohms to 177 ohms with 15MHz modulation. The maximum obtainable RF power of all devices tested using 50 ohm and 100 ohm loads at 15MHz is 15.73dBm and 17.83dBm, respectively. The maximum obtainable RF power using a 177 ohm load for all devices tested is 17.67dBm, which is slightly smaller than that obtained with a 100 ohm load. A measurement procedure for RF power extraction at microwave frequencies is also described. Quarter-wavelength 70.71 ohm thin film coplanar waveguides are designed to transform 50 ohms to a higher impedance of 100 ohms for measurements of improved RF power extraction at 3GHz and 7GHz.

The aim of this work was double-balanced mixer implementation, which will be used like laboratory equipment. This thesis deals with design of the double-balanced mixer from first theoretical principles to a practical design of a laboratory equipment. For the practical design the integrated mixer SA612 was used. Input signal to the mixer up to 500 MHz frequency can be used. For required operation external oscillator and fifth-order low pass filter were constructed. Oscillator was designed for fixed frequency 32 MHz. Fifth-order low pass filter was inserted between the mixer and the oscillator, because of filtering higher harmonics. The second aim of the work was measuring double-balanced mixer basic parameters, such as Compression Point (P-1dB) and Intercept Point (IP3). For the IP3 measurement, another one device was required. It consists of the power combiner for mixing two frequency close signals and third-order bandpass filter, which selects required frequency band. Finally, the laboratory equipment was fabricated and its real parameters were measured.

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.