The CDMA standard operating over the wireless environment along with various other wireless standards places stringent specifications on the RF Front end. Due to possible large interference signal tones at the receiver end along with the carrier, the Low Noise Amplifier (LNA) is expected to provide high linearity, thus preventing the intermodulation tones created by the interference signal from corrupting the carrier signal. The research focuses on designing a novel LNA which achieves high linearity without sacrificing any of its specifications of gain and Noise Figure (NF). The novel LNA proposed achieves high linearity by canceling the IM3 tones in the main transistor in both magnitude and phase using the IM3 tones generated by an auxiliary transistor. Extensive Volterra series analysis using the harmonic input method has been performed to prove the concept of third harmonic cancellation and a design methodology has been proposed. The LNA has been designed to operate at 900MHz in TSMC 0.35um CMOS technology. The LNA has been experimentally verified for its functionality. Linearity is usually measured in terms of IIP3 and the LNA has an IIP3 of +21dBm, with a gain of 11 dB, NF of 3.1 dB and power consumption of 22.5 mW.

Addressing the high cost of RF instrumentation has motivated significant research activity, where researchers have proposed various non-standard and alternative test methods of RF circuits to mitigate high test cost. This dissertation describes a test methodology for RF receivers, whereby simple digital circuits comprise the core of the otherwise complex and costly broadband RF/analog signal generation. The proposed test methodology relies on a digital clock, commonly available to RF ICs for the purpose of digital communication, to generate the broadband RF stimulus needed for the receiver analog tests. The test method also utilizes commonly available baseband signal digitization (on-chip or off-chip) to acquire the baseband signal. It then relies on sophisticated, but inexpensive, signal processing to extract and compute standard RF performance parameters, like gain, noise figure (NF), and input-referred third-order intercept point (IIP3). In addition, the test method can extract important baseband (BB) parameters like the BB filter 3 dB bandwidth (BW), filter rejection at specific BB frequencies, or the BB filter profile. The motivation behind the proposed test methodology can be categorized as both architectural and cost reduction-oriented. Architecturally, the proposed test method aims at shifting the complexity involved in the test of RF receivers from the hardware (input) RF signal generation side to the signal processing done on the (output) baseband side. The process of shifting the complexity from the hardware design side to the signal processing side involves significant complex and sophisticated analysis, which is part of this dissertation. Cost-wise, the proposed test methodology enables the use of digital automatic test equipment (ATE) with limited baseband capability, instead of the full standard RF testers. Such a step reduces the initial tester cost and impacts the cost/sec figure spent on test for the life of the ATE tester, thus leading to test cost reduction. / text

abstract: Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors, or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance, is challenging. In this work, a BiST technique to compute transmitter IQ imbalances using measurements out of a self-mixing envelope detector is proposed. Both the linear and non linear parameters of the RF transmitter path are extracted successfully. We first derive an analytical expression for the output signal. Using this expression, we devise test signals to isolate the effects of gain and phase imbalance, DC offsets, time skews and system nonlinearity from other parameters of the system. Once isolated, these parameters are calculated easily with a few mathematical operations. Simulations and hardware measurements show that the technique can provide accurate characterization of IQ imbalances. One of the glaring advantages of this method is that, the impairments are extracted from analyzing the response at baseband frequency and thereby eliminating the need of high frequency ATE (Automated Test Equipment). / Dissertation/Thesis / M.S. Electrical Engineering 2012

As wireless devices and radar systems become more ubiquitous, there is a growing need for wideband multi-standard RF-SOCs. To enable the advantages of multi-standard systems, reconfigurable RF front ends are needed. Because of the large number of RF signals in wideband systems, tunability and linearity become important parameters. Prior work has shown tunable LC filters to be advantageous in the microwave regime. A balanced-to-unbalanced (balun) transformation circuit is required to support the differential nature of a tunable LC filter. An active balun that also performs as a transconductor to drive the LC tank would relax the design requirement for the LNA and remove a passive balun that would have to precede the LNA. This thesis discusses the linearization of active baluns and presents a comparison between two 4 to 7 GHz tunable BPF designs with active baluns implemented in 0.18 μm SiGe BiCMOS technology. Fourth order filtering is achieved by subtracting two 2nd order LC-tanks. This approach allows 3-dB bandwidth to be tunable from 10% to 20%. In each design, a linearized input active balun is employed to drive the LC-tanks from a single-ended input while preserving noise figure and IIP3 performance. Two different linearization techniques are applied for the balun designs. Simulated NF ranges from 7.5 to 13 dB and IIP3 averages about 5 dBm with the peak value of 21 dBm. / Master of Science / As wireless devices and radar systems become more ubiquitous, there is a growing need for Radio Frequency (RF) integrated circuits that can support multiple frequency bands and standards. Because of the large number of RF signals, robust tunability and power handling of the electronics become important parameters. Power handling is important because the amplifier and the filter can generate distortions if the power going through them becomes too high. Prior work has shown integrated tunable inductor-capacitor (LC) resonance based filters to be advantageous in the microwave frequency regime compared to integrated switched capacitor based filters. A balancedto-unbalanced (balun) conversion of the RF signals is needed to support the differential nature of the LC resonators. This thesis discusses transistor-based balun designs that can be integrated into front-end LC filter chips. The goal is to reduce distortion in the filter under the present of large number of RF signals and to keep noise of the circuit in reasonable range. The designs are implemented in 0.18 μm SiGe BiCMOS integrated circuit technology and simulated in commercial computer aided design software; predicted performance is competitive with the state of the art. The fabricated chips will be characterized in future work.

The objective of the proposed research is to understand the design and reliability of RF front-end building blocks using SOI CMOS and SiGe BiCMOS technologies for high dynamic-range applications. This research leads to a comprehensive understanding of dynamic range in SOI CMOS devices and contributes to knowledge leading to improvement in overall dynamic range and reliability of RF building blocks. While the performance of CMOS transistors has been improving naturally with scaling, this work aims to explore the possibilities of improvement in RF performance and reliability using standard layouts (that don't need process modifications). The total-ionizing dose tolerance of SOI CMOS devices has been understood with extensive measurements. Furthermore, the role of body contacts in SOI technology is understood for dynamic range performance improvement. In this work, CMOS low-noise amplifier design for high linearity WLAN applications and its integration with RF switch on the same chip is presented. The LNA and switches designed provide state-of-the-art performance in silicon based technologies. Further, the work aims to explore applications of SiGe HBT in the context of highly linear and reliable RF building blocks. The RF reliability of SiGe HBT based RF switches is investigated and compared with CMOS counterparts. The inverse-mode operation of SiGe HBT based switches is understood to give considerably higher linearity.

No description available.

This thesis presents novel radio frequency microelectromechanical (RF MEMS) circuits based on the three-dimensional (3-D) micromachined coplanar transmission lines whose geometry is re-configured by integrated microelectromechanical actuators. Two types of novel RF MEMS devices are proposed. The first is a concept of MEMS capacitors tuneable in multiple discrete and well-defined steps, implemented by in-plane moving of the ground side-walls of a 3-D micromachined coplanar waveguide transmission line. The MEMS actuators are completely embedded in the ground layer of the transmission line, and fabricated using a single-mask silicon-on-insulator (SOI) RF MEMS fabrication process. The resulting device achieves low insertion loss, a very high quality factor, high reliability, high linearity and high self actuation robustness. The second type introduces two novel concepts of area efficient, ultra-wideband, MEMS-reconfigurable coupled line directional couplers, whose coupling is tuned by mechanically changing the geometry of 3-D micromachined coupled transmission lines, utilizing integrated MEMS electrostatic actuators. The coupling is achieved by tuning both the ground and the signal line coupling, obtaining a large tuneable coupling ratio while maintaining an excellent impedance match, along with high isolation and a very high directivity over a very large bandwidth. This thesis also presents for the first time on RF nonlinearity analysis of complex multi-device RF MEMS circuits. Closed-form analytical formulas for the IIP3 of MEMS multi-device circuit concepts are derived. A nonlinearity analysis, based on these formulas and on  measured device parameters, is performed for different circuit concepts and compared to the simulation results of multi-device  conlinear electromechanical circuit models. The degradation of the overall circuit nonlinearity with increasing number of device stages is investigated. Design rules are presented so that the mechanical parameters and thus the IIP3 of the individual device stages can be optimized to achieve a highest overall IIP3 for the whole circuit.The thesis further investigates un-patterned ferromagnetic NiFe/AlN multilayer composites used as advanced magnetic core materials for on-chip inductances. The approach used is to increase the thickness of the ferromagnetic material without increasing its conductivity, by using multilayer NiFe and AlN sandwich structure. This suppresses the induced currents very effectively and at the same time increases the ferromagnetic resonance, which is by a factor of 7.1 higher than for homogeneous NiFe layers of same thickness. The so far highest permeability values above 1 GHz for on-chip integrated un-patterned NiFe layers were achieved. / <p>QC 20140328</p>

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.