On assiste aujourd’hui à une évolution des systèmes électroniques nomades vers des fonctionnalités plus avancées. Cette complexification des systèmes électroniques nomades nécessite une augmentation de la puissance de calcul des puces électronique, ce qui se peut se traduire par une utilisation d’une technologie CMOS agressive, mais qui se complète aujourd’hui par une technique appelée intégration 3D. Il ne s’agit donc plus d’une évolution classique à l’échelle du transistor suivant la loi de Moore mais à celle de l’échelle plus large du boîtier / système, on parle alors de la loi de « More than Moore ». L’empilement tridimensionnel (3D) des puces électroniques engendre une augmentation de la densité de puissance totale dissipée par unité de surface de l’empilement final. Cette puissance, résultant essentiellement de l’effet joule dans les transistors et l’interconnexion, est une source de chaleur qui contribue à l’augmentation de la température globale de la puce. L’objectif global de cette thèse est d’étudier les échanges thermiques dans un empilement de puces 3D durant leur fonctionnement. On s’attachera à comprendre les effets géométriques ou matériaux de l’empilement ainsi que l’impact du placement des TSV, Bumps ... sur ces échanges thermiques. L’étude s’appuie sur des simulations numériques validées par des mesures expérimentales sur des empilements 3D. Ces études numérique et expérimentale auront comme finalité de déduire des règles de dessin thermiques qui seront validées sur le dessin de circuits basiques ou plus complexes. Dans la suite, ces différents objectifs seront motivés et abordés en détail. L’établissement d’un modèle thermique basé sur des simulations en éléments finis d’un procédé industriel CMOS 65 nm 3D permettra d’aborder le problème de modélisation de la manière la plus précise possible. En effet, les précédentes simulations ont utilisé des modèles compacts – donc de moindre précision que les éléments finis – et un procédé générique qui ne reflète pas toutes les propriétés des matériaux, et en particulier celles des interfaces. Les résultats ainsi obtenus seront validés par des mesures sur des puces empilées réalisées dans le procédé considéré. Dans cette partie expérimentale, l’objectif est de déterminer une cartographie de la température dans un empilement 3D en utilisant des capteurs embarqués dans le silicium, et ce sous différentes conditions d’opération de la puce 3D. Il en ressortira un modèle numérique validé et calibré par des mesures expérimentales. / Today we are witnessing an evolution of mobile electronic systems to more advanced features. The complexity of mobile electronic systems requires an increase in computing power of electronic chips, which can lead to the use of aggressive CMOS technology, but which now completed with a technique called 3D integration. It is more of a classical evolution across the transistor following Moore's law but that of the wider scale of the packaging / system, it is called the law of "More than Moore". Three dimensional (3D) stack of electronic chip generates an increase in the density of total power dissipated per unit area of the final stack. This power, essentially resulting in the Joule effect transistors and interconnection, is a source of heat which contributes to increase the overall temperature of the chip. The global objective of this thesis is to study the heat transfer in a 3D stack of chips during operation. We will seek to understand the geometric or materials effects of the stack and the impact of the placement of TSV, Bumps ... on these heat exchanges. The study is based on numerical simulations validated by experimental measurements on 3D stacks. These numerical and experimental studies have as a goal to deduce thermal design rules that will be validated in the drawing of basic or more complex circuits. In the following, these goals will be motivated and discussed in detail. The establishment of a thermal model based on finite element simulations of an industrial process 3D CMOS 65 nm will address the problem of modelling the most accurate way possible. Indeed, previous simulations used compact models - so that the lower accuracy of finite elements - and a generic method that does not reflect all of the properties of materials, and in particular interfaces. The results obtained will be validated by measurements on stacked chips carried out within the process concerned. In the experimental part, the objective is to determine a thermal mapping in a 3D stack using sensors embedded in the silicon, and under different conditions of 3D chip process. This will provide a numerical model validated and calibrated by experimental measurements.

L'impact des interconnections d'un circuit intégré sur les performances et la consommation est de plus en plus important à partir du nœud CMOS 28 nm et au-delà, ayant pour effet de minimiser de plus ne plus la loi de Moore. Cela a motivé l'intérêt des technologies d'empilement 3D pour réduire l'effet des interconnections sur les performances des circuits. Les technologies d'empilement 3D varient suivant différents procédés de fabrication d'où l'on mettra en avant la technologie Trough Silicon Via (TSV) – Collage Cuivre-Cuivre (Cu-Cu) et 3D Monolithique. TSV et Cu-Cu présentent des diamètres d'interconnexions 3D de l'ordre de 10 µm tandis que le diamètre d'une interconnexion 3D Monolithique est 0.1 µm, c'est-à-dire cent fois plus petit. Un tel diamètre d'interconnexion créée de nouveaux challenge en terme de conception de circuit intégré numérique. Dans ce contexte, notre objectif est de proposer des méthodologies de conception de circuits 3D innovantes afin d'utiliser au mieux la densité d'intégration possible et d'évaluer efficacement les gains en performance, surface et consommation potentiels de ces différentes technologies d'empilement par rapport à la conception de circuit 2D.Trois contributions principales constituent cette thèse : La densité d'intégration offerte par les technologies d'empilement étudiées laisse le possibilité de revoir la topologie des cellules de bases en les concevant directement en 3D. C'est ce qui a été fait dans l'approche Cellule sur Buffer (Cell-on-Buffer – CoB), en empilant la fonction logique de base d'une cellule sur l'étage d'amplification. Les simulations montrent des gains substantiels par rapport aux circuits 2D. On a imaginé par la suite désaligner les niveaux d'alimentation de chaque tranche afin de créer une technique de Multi-VDD adaptée à l'empilement 3D pour réduire encore plus la consommation des circuits 3D.Dans un deuxième temps, le partitionnement grain fin des cellules a été étudié. En effet au niveau VLSI, quand on conçoit un circuit de plusieurs milliers voir million de cellules standard en 3D, se pose la question de l'attribution de telle ou telle cellule sur la tranche haute ou basse du circuit 3D afin d'accroitre au mieux les performances et consommation du circuit 3D. Une méthodologie de partitionnement physique est introduite pour cela.Enfin un environnement d'évaluation des performances et consommation des technologies 3D est présenté avec pour objectif de rapidement tester les gains possibles de telle ou telle technologie 3D tout en donnant des directives quant à l'impact des certains paramètres technologiques 3D sur les performances et consommation. / Scaling limitations of advanced technology nodes are increasing and the BEOL parasitics are becoming more dominant. This has led to an increasing interest in 3D technologies to overcome such limitations and to continue the scaling predicted by Moore's Law. 3D technologies vary according to the fabrication process which creates a wide spectrum of technologies including Through-Silicon-VIA (TSV), Copper-to-Copper (CuCu) and Monolithic 3D (M3D). TSV and CuCu provide 3D contacts of pitch around 5-10um while M3D scales down 3D via pitch extremely to 0.11um. Such high-density capability of Monolithic 3D technology creates new design paradigms. In this context, our objective is to propose innovative design methodologies to well utilize M3D technology and introduce a technology assessment framework to evaluate different M3D technology parameters from design perspective.This thesis can be divided into three main contributions. As creating 3D standard cells become achievable thanks to M3D technology, a new 3D standard cell approach has been introduced which we call it ‘3D Cell-on-Buffer' (3DCoB). 3DCoB cells are created by splitting 2D cells into functioning gates and driving buffers stacked over each other. The simulation results show gain in timing performances compared to 2D. By applying an additionally Multi-VDD low-power approach, iso-performance power gain has been achieved. Afterwards cell-on-cell design approach has been explored where a partitioning methodology is needed to distribute cells between different tiers, i.e. determine which cell is placed on which tier. A physical-aware partitioning methodology has been introduced which improves power-performance-area results comparing to the state-of-the-art partitioning techniques. Finally a full high-density 3D technology assessment study is presented to explore the trade-offs between different 3D technologies, block complexities and partitioning methodologies.

Le travail de doctorat réalisé s'attache à étudier les nouveaux types d'interconnexions comme les TSV (Through Silicon Via), les lignes de redistribution (RDL) et les piliers de cuivre (Cu-Pillar) présentes dans le domaine de l'intégration 3D en microélectronique avancée, par exemple pour des applications de type « imager » où une puce « capteur optique » est empilée sur une puce « processeur ». Afin de comprendre et quantifier le comportement électrique de ces nouveaux composants d'interconnexion, une première problématique de la thèse s'articulait autour de la caractérisation électrique, sur une très large bande de fréquence (10 MHz - 60 GHz) de ces éléments, enfouis dans leurs environnements complexes d'intégration, en particulier avec l'analyse de l'impact des pertes dans les substrats de silicium dans une gamme de conductivités allant de très faible (0 S/m) à très forte (10 000 S/m). Par la suite, une nouvelle problématique prend alors naissance sur la nécessité de développer des modèles mathématiques permettant de prédire le comportement électrique des interconnexions 3D. Les modèles électriques développés doivent tenir compte des pertes, des couplages ainsi que de certains phénomènes liés à la montée en fréquence (courants de Foucault) en fonction des caractéristiques matériaux, des dimensions et des architectures (haute à faible densité d'intégration). Enfin, à partir des modèles développés, une dernière partie propose une étude sur les stratégies de routage dans les empilements 3D de puces à partir d'une analyse sur l'intégrité de signaux. En opposant différents environnements, débit de signaux binaires ou dimensions des TSV et des RDL des conclusions émergent sur les stratégies à adopter pour améliorer les performances des circuits conçus en intégration 3D. / The aim of this doctoral work is to study the new kind of interconnections like TSV (Through Silicon Via), redistribution lines (RDL) and copper pillars used in 3D integration context in advanced microelectronic components. An example of 3D integration application could be an imager designed by staking an optical sensor chip upon a processor chip. In order to understand and quantify the electrical behaviour of these new interconnection components, the first issue was about electrical characterization in a very wide frequency band (10 MHz - 60 GHz) of these elements, buried in their complex environment, in particular with the analysis of the silicon substrate loss impact which can be found in a wide band of conductivities from very low (0 S/m) to very high (10 000 S/m). Subsequently, a second issue appears from the need to develop mathematical models to predict the electrical behavior of 3D interconnects. The developed models have to take into account losses, coupling effects and some phenomena appearing with the rise of frequency (eddy currents) according to material characteristics, dimensions and architecture (from high to low density of integration). Finally, based on developed models, the last part presents a study on routing strategies in the 3D stacking chip from the analysis of signal integrity. By contrasting various environments, binary signals flow or dimensions of TSV and RDL, conclusions emerge on the best strategies to use to improve performances of circuits designed in 3D integration.

Ces dernières années, l’évolution de la taille des circuits intégrés a été dirigée par la loi de Moore conduisant à des noeuds technologiques de 22 nm et en-deçà. Cependant, les problématiques de performances, de taille et de coût des composants rendent cette conjecture difficile à suivre. La tendance de diversification appelée « More than Moore » consiste à intégrer des fonctions analogiques avec des technologies CMOS dans le but d’optimiser les coûts.L'une de ses technologies clés est le TSV, qui maintient le contact entre deux niveaux de composants. Leurs facteurs de forme devenant de plus en plus élevés, les techniques de dépôts standards par iPVD sont proches de leurs limites. De plus, les méthodes de caractérisation usuelles ne sont pas adaptées à ces structures.La première partie de cette thèse sera dédiée au développement des procédés de dépôt de la barrière de diffusion du cuivre par MOCVD à basse température pour s’adapter aux divers schémas d'intégration de type via middle et via last. La deuxième partie sera consacrée à l’élaboration des protocoles avancés de caractérisation des films dans ces structures afin d’étudier leurs comportements en intégration. / For the past years, Moore’s law has pointed mainstream microelectronics, driving integrated circuits down to 22 nm and below. Yet, performance, dimension and cost issues make it difficult to follow the trend. Integrating analog functions into CMOS-based technologies enables cost-optimized systems solutions. These diversified tendencies are known as “More than Moore”. One of the key technologies of this trend is the TSV, which maintains the contact between two components.The increasing aspect ratio of via made it critical to obtain a continuous, conformal coverage of the copper diffusion barrier layer using iPVD.In the first part of this thesis, a promising deposition technique by MOCVD has been developed at low temperature to fulfill various integration schemes including via last and via middle processes.Characterizations of the behavior of these materials in the TSV then became a great challenge in order to handle the integration protocol. Working at theses scales makes standard methods limited to evaluate the intrinsic properties inside the TSV. In the second part, the implementations of advanced characterization into these structures were carried out.

The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects. The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages. The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality. The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead. The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.

A key challenge for three dimensional (3D) integrated circuits (ICs) is thermal management. There are two main thermal challenges in typical 3D ICs. First, in the homogeneous integration with multiple high-power tiers, an effective cooling solution that scales with the number of dice in the stack is needed. Second, in the heterogeneous integration, an effective thermal isolation solution is needed to ‘protect’ the low-power tier from the high-power tier. This research focuses to address these two thermal challenges through hybrid microfluidic cooling and thermal isolation technologies. Within-tier microfluidic cooling is proposed and demonstrated to cool a stack with multiple high-power tiers. Electrical thermal co-analysis is performed to understand the trade-offs between through silicon via (TSV) parasitics and heat sink performance. A TSV-compatible micropin-fin heat sink is designed, fabricated and thermally characterized in a single tier, and benchmarked with a conventional air-cooled heat sink. The designed heat sink has a thermal resistance of 0.269 K·cm2/W at a flow rate of 70 mL/min. High aspect ratios TSVs (18:1) are integrated in the micropin-fins. Within-tier microfluidic cooling is then implemented in 3D stacks to emulate different heating scenarios, such as memory-on-processor and processor-on-processor. Air gap and mechanically flexible interconnects (MFIs) are proposed for the first time to decrease the vertical thermal coupling between high-power (e.g. processor) and low-power tiers (e.g. memory or nanophotonics). A two-tier testbed with the proposed thermal isolation technology is designed, fabricated and tested. Compared with conventional 3D integration approach, thermal isolation technology helps reduce the temperature at a fixed location in the low-tier by 12.9 °C. The resistance of a single MFI is measured to be 46.49 mΩ.

Electronic devices today are an integral part of human life thanks to state-of-the- art complementary metal oxide semiconductor (CMOS) technology. The progress in this area can be attributed to miniaturization driven by Moore’s Law. Further advancements in electronics are under threat from physical limits in dimensional scaling and hence new roadmaps for alternative materials and technologies are chased. Furthermore, the current era of Internet of things (IoT) and Internet of everything (IoE) has broaden the horizon to a plethora of unprecedented applications. The most prominent emerging fields are flexible and stretchable electronics. There has been significant progress in developments of flexible sensors, transistors, and alternative materials, etc. Nonetheless, there remains the unaddressed challenges of matching performance of the status-quo, packaging, interconnects, and lack of pragmatic integration schemes to readily complement existing state-of-the-art technology. In this thesis, a pragmatic heterogeneous integration strategy is presented to obtain high-performance 3D electronic systems using existing CMOS based integrated circuit (IC). Critical challenges addressed during the process are: reliable flexible interconnects, maximum area efficiency, soft-polymeric packaging, and heterogeneous integration compatible with current CMOS technology. First, a modular LEGO approach presents a novel method to obtain flexible electronics in a lock-and-key plug and play manner with reliable interconnects. A process of converting standard rigid IC into flexible LEGO without any performance degradation with a high-yield is shown. For the majority of healthcare and other monitoring applications in IoT, sensory array is used for continuous monitoring and spatiotemporal mapping activities. Here we present ultra-high-density sensory solution (1 million sensors) as an epitome of density and address each of the associated challenges. A generic heterogeneous integration scheme has been presented to obtain physically flexible standalone electronic system using 3D-coin architecture. This 3D-coin architecture hosts sensors on one side, readout circuit and data processing units embedded in the polymer, and the other side is reserved for antenna and energy harvester (photovoltaic). This thin platform (~ 300 μm) has achieved bending radius of 1 mm while maintaining reliable electrical interconnection using through-polymer-via (TPV) and soft-polymeric encapsulation. This coin integration scheme is compatible with existing CMOS technology and suitable for large scale manufacturing. Lastly, a featherlight non-invasive ‘Marine-Skin’ platform to monitor deep-ocean monitoring is presented using the heterogeneous integration scheme. Electrical and mechanical characterization has been done to establish reliability, integrity, robustness, and ruggedness of the processes, sensors, and multisensory flexible system.

No description available.

The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.

Dans cette thèse, nous étudions les architectures 3D NoC grâce à des implémentations de conception physiques en utilisant la technologie 3D réel mis en oeuvre dans l'industrie. Sur la base des listes d'interconnexions en déroute, nous procédons à l'analyse des performances d'évaluer le bénéfice de l'architecture 3D par rapport à sa mise en oeuvre 2D. Sur la base du flot de conception 3D proposé en se concentrant sur la vérification temporelle tirant parti de l'avantage du retard négligeable de la structure de microbilles pour les connexions verticales, nous avons mené techniques de partitionnement de NoC 3D basé sur l'architecture MPSoC y compris empilement homogène et hétérogène en utilisant Tezzaron 3D IC technlogy. Conception et mise en oeuvre de compromis dans les deux méthodes de partitionnement est étudiée pour avoir un meilleur aperçu sur l'architecture 3D de sorte qu'il peut être exploitée pour des performances optimales. En utilisant l'approche 3D homogène empilage, NoC topologies est explorée afin d'identifier la meilleure topologie entre la topologie 2D et 3D pour la mise en œuvre MPSoC 3D sous l'hypothèse que les chemins critiques est fondée sur les liens inter-routeur. Les explorations architecturales ont également examiné les différentes technologies de traitement. mettant en évidence l'effet de la technologie des procédés à la performance d'architecture 3D en particulier pour l'interconnexion dominant du design. En outre, nous avons effectué hétérogène 3D d'empilage pour la mise en oeuvre MPSoC avec l'approche GALS de style et présenté plusieurs analyses de conception physiques connexes concernant la conception 3D et la mise en œuvre MPSoC utilisant des outils de CAO 2D. Une analyse plus approfondie de l'effet microbilles pas à la performance de l'architecture 3D à l'aide face-à-face d'empilement est également signalé l'identification des problèmes et des limitations à prendre en considération pendant le processus de conception.