This thesis aimed to investigate ways to conduct participatory research practices that would gain knowledge of participants' relationships and experiences with/in their physical home environment by using a design probe. Through the probe, a new approach to participatory design research was formulated. This approach gives agency to participants through elements of auto-ethnography, thus shifting the traditional power structures that often exist between participants and designers. This new type of research could yield greater intimacy and mutuality between designers and their participants. Due to this, it has the potential to be meaningful when designing for the home environment, and therefore can be used for research and design within the Internet of Things.

Une plateforme de conception est une solution totale qui permet à une équipe de conception de développer un système sur puce. Une telle plateforme se compose d'un ensemble de bibliothèques et de circuits réutilisables (IPs), d'outils de CAO et de kits de conception en conformité avec les flots de conception et les méthodologies supportés. Les spécifications de ce type de plateforme offrent un large éventail d'informations, depuis des paramètres de technologie, jusqu'aux informations sur les outils. En outre, les développeurs de bibliothèque/IP ont des difficultés à obtenir les données nécessaires à partir ces spécifications en raison de leur informalité et complexité. Dans cette thèse, nous proposons des méthodologies, des flots et des outils pour formaliser les spécifications d'une plateforme de conception et les traiter. Cette description proposée vise à être utilisée comme une référence pour générer et valider les bibliothèques et les IPs. Nous proposons un langage de spécification basé sur XML (nommé LDSpecX). De plus, nous présentons une méthode basée sur des références pour créer une spécification fiable en LDSpecX et des mots-clés basés sur des tâches pour en extraire les données efficacement. A l'aide des solutions proposées, nous développons une plateforme de spécification. Nous développons une bibliothèque de cellules standard en utilisant cette plateforme de spécification. Nous montrons ainsi que notre approche permet de créer une spécification complète et cohérente avec une réduction considérable du temps. Cette proposition comble également l'écart entre les spécifications et le système automatique existant pour le développement rapide de bibliothèques/IPs. / A design platform (DP) is a total solution to build a System-On-Chip (SOC). DP consists of a set of libraries/IPs, CAD tools and design kits in conformity with the supported design flows and methodologies. The DP specifications provide a wide range of information from technology parameters like Process-Voltage-Temperature (PVT) corners to CAD tools’ information for library/IP development. However, the library/IP developers have difficulties in obtaining the desired data from the existing specifications due to their informality and complexity. In this thesis, we propose methodologies, flows and tools to formalize the DP specifications for their unification and to deal with it. The proposed description is targeting to be used as a reference to generate and validate libraries (standard cells, I/O, memory) as well as complex IPs (PLL, Serdes, etc.). First, we build a suitable data model to represent all required information for library/IP development and then propose a specification language named Library Development Specification based on XML (LDSpecX). Furthermore, we introduce a reference-based method to create a reliable specification in LDSpecX and task-based keywords to efficiently extract data from it. On the basis of the proposed solutions, we develop a specification platform. Experimentally, we develop a standard cell library from the specification creation to library validation by using the specification platform. We show that our approach enables to create a complete and consistent specification with a considerable reduction in time. It also bridges the gap between the specification and current automatic system for rapid library/IP development.

Cette thèse s’inscrit dans le contexte des systèmes embarqués qui sont qualifiés de complexes car leur développement nécessite une expertise pluridisciplinaire. Une stratégie de développement s'avère incontournable pour concevoir ces systèmes. Cette complexité est encore plus sévère dans le domaine du développement des systèmes embarqués pour UAV.Nous proposons une approche de développement orientés systèmes embarqués basés COTS. Cette démarche combine plusieurs méthodes issues du génie logiciel classique que nous avons adapté aux systèmes embarqués. Nous avons appliqué cette approche pour développer un système de capteurs embarqués pour un micro-UAV à voilures fixes.Le système embarqué développé a été déployé sur un robot classique, une bicyclette et un modèle réduit d'avion. L'objectif est de valider la consistance des données capteurs, compte tenu de la disparité des dynamiques entres ces systèmes. Ces expériences ont permis de mettre en évidence des similitudes théoriques entre ces 3 dynamiques. L'objectif est de pouvoir valider des systèmes embarqués pour UAV sur des plateformes à moindre coût et à moindre complexité, tout en garantissant la consistance des données capteurs et leur interprétation par rapport aux trois plateformes. Nous avons construit, aussi, une plateforme de simulation dont l’objectif est de supporter l’approche de développement proposée. Nous avons utilisé cette plateforme pour concevoir un système de contrôle, guidage et navigation pour un UAV à voilures fixes. Ces applications montrent, ainsi, l’efficacité de l’approche de développement proposée. / This thesis tackles the problem of embedded system design, which are often qualified as complex systems because their development requires multidisciplinary expertise. A development strategy is then essential to design these systems. As an application, we focused on UAV embedded systems, which show very severe development constraints.We propose a development approach oriented COTS-based embedded systems. This approach combines several methods from classic software engineering filed that we have adapted for embedded systems. We applied this approach to develop an embedded sensors system for a micro fixed wings UAVs.The designed embedded system has been deployed on an UAV, a mobile and a bicycle. The aim is to validate the UAV embedded system using a lower cost platforms and with less complexity, while ensuring sensors data consistency and interpretation regarding the dynamic of the three platforms. These experiments highlight the theoretical similarities between those three dynamics. Furthermore, we built a simulation platform that aims to support the proposed development approach. We used this platform to design a control, guidance and navigation system for a fixed wings UAV. These applications show the effectiveness of the proposed development approach.

Dans le domaine de la détection et du suivi d'obstacles pour les systèmes ADAS (Advanced Driver Assistance System) basés vision, il est nécessaire d'assurer la localisation à court terme du véhicule. Le SLAM (Simultaneous Localization and Mapping) basé vision propose de résoudre ce problème en combinant l’estimation de l’état du véhicule (pose dans un repère local et vitesses) et une modélisation incrémentale de l’environnement. Ce dernier est perçu par l'extraction de caractéristiques locales (points d'intérêt) dans une séquence d'images et leur suivi au cours du temps pour permettre la construction incrémentale d'une carte d'amers. Cette tâche de perception engendre une importante charge de calcul qui affecte très significativement la latence et la cadence du système. Les méthodologies de co-design permettent de concevoir une architecture mixte de calcul pour l“exécution d'une application particulière. Dans ce type d'architecture, l'utilisation d'accélérateurs matériels permet d'améliorer significativement les performances (temps d'exécution, encombrement, consommation). Le ZynQ (Xilinx) propose une architecture de prototypage mixte comprenant un processeur dual-core associé à des ressources matérielles configurables. L'objectif de cette thèse est donc de proposer une implémentation co-design d'un SLAM basé vision par la conception d'accélérateurs pour les opérations de vision afin de satisfaire les contraintes en performances des systèmes ADAS embarqués. La première contribution des travaux est la conception de cette chaîne complète 3D EKF-SLAM à l'aide une approche co-design. Nous avons défini et validé, selon notre méthodologie de conception, le choix d'une architecture Hardware-in-theloop (HIL) afin de valider les différentes itérations de conception. La seconde contribution est l'intégration de modules matériels dédiés pour accélérer les traitements de perception visuelle de cette chaîne (détection, description et mise en correspondance de points d’intérêt). / In the field of obstacle detection and tracking for vision-based ADAS (Advanced Driver Assistance System), it is necessary to perform short-term vehicle localisation. Vision based SLAM (Simultaneous Localization and Mapping) solves this problem by combining the vehicle state estimation (local pose and speeds) and an incremental modelling of the environment. The environment is perceived by extracting features (interest points) in a sequence of images and tracking them over time to allow an incremental landmarks map construction. The perception step leads to an important computational load which affects very significantly the system latency and throughput. Co-design methodologies allow to design a mixed processing architecture optimized for a specific application In this type of architecture, the use of hardware accelerators allows for great performance increase (throughput, memory size, power consumption). The ZynQ (Xilinx) provides a prototyping mixed-architecture including a dual-core microprocessor combined with configurable hardware resources. The goal of this thesis is to propose a co-design implementation of a vision-based SLAM processing chain involving hardware accelerators for image processing in order to meet the constraints of an embedded ADAS system. The first contribution is the design of a complete 3D EKF-SLAM processing chain thanks to a codesign approach. We defined and validated, according to the followed co-design approach, the choice of a Hardware-in-the-loop (HIL) architecture to validate the different design iterations. The second contribution is the integration of dedicated hardware modules to accelerate the visual perception computations of this processing chain (features detection, description and matching).

Tato práce popisuje navrženou metodologii pro návrh systémů odolných proti poruchám v FPGA schopnou ochránit systém před projevy přechodných a trvalých poruch. Oprava přechodné poruchy je prováděna částečnou dynamickou rekonfigurací. Oprava omezeného počtu trvalých poruch je založena na použití odolných architektur využívajících menší množství zdrojů než předchozí použitá architektura. Vadná část FPGA tak není dále využívána. Tato technika je založena na použití předkompilovaných konfigurací uložených v externí paměti. Pro snížení paměťových nároků pro uložení konfiguračních bitových posloupností je použita technika relokace.

This is a documentation of a programmatic design approach, moving through different levels of an established practice of grassroots activism. The text frames an open-ended, exploratory methodology, as four stages of investigation, trying to find possible ways to shape and increase understanding of, and facilitate a process, of co-designing a practice. It presents the experience of looking for opportunities for counter-narration, as contribution to an activist cause, and questioning the role, purpose and approach of a designer in a grassroots activist environment.

High Level Synthesis (HLS) is a methodology to translate a model developed in a high abstraction layer, e.g. C/C++/SystemC, that describes the algorithm into a Register-Transfer level (RTL) description like Verilog or VHDL. The resulting RTL description from the translation is subject to multiple user-controlled directives and an internal design space exploration algorithm specific to the toolchain used. HLS allow designers to focus on the behaviour of the design at a higher abstraction compared to the behavioural modelling available within the Hardware Description Language (HDL) as the compiler decides the movement of data and timing in the resulting design. Ericsson uses a legacy Advanced Peripheral Bus (APB) like interface called Memory/Register Interface (MIRI) interface for data movement in a subsystem of one of their Application-Specific Integrated Circuit (ASIC). The thesis attempts to upgrade the protocol to the more performant ARM Advanced Microcontroller Bus Architecture (AMBA) protocols’ Advanced High-performance Bus (AHB) or Advanced eXtensible Interface (AXI) interfaces. SystemC provides a host of functionalities to define the complete behaviour of the circuit at a high level of abstraction. This thesis will explore the effect of the structuring SystemC models on their synthesis, and perform design space exploration to understand the best design methodology to adopt in a SystemC model design and compare the models based on the final synthesis metrics like area, timing, and register counts. The toolchain for the thesis will be the Stratus HLS compiler developed by Cadence. Stratus supports all synthesizable constructs of SystemC. Most HLS research focuses on improving Design Space Exploration algorithms used internally in the HLS tools. However, designers can utilize algorithm structuring to provide the HLS engines with a better starting point. In this thesis, the Stratus toolchain will be used to experiment with different models with equivalent behaviour and performance. Thereafter, extract which constructs used in the models are optimal for allowing the internal design space exploration algorithm to perform in the best way possible. / HLS är en metod för att översätta en modell utvecklad på hög abstraktionsnivå t.ex. C/C++/SystemC som beskriver algoritmen på registeröverföringsnivå (RTL) som Verilog eller VHDL. Den resulterande RTL-beskrivningen utsätts för flera användarkontrollerade direktiv och en intern Design Space Exploration (DSE) algoritm, vilken är specifik för den verktygskedja som används. Detta gör det möjligt för en designer att fokusera på konstruktion beteende på en högre abstraktionsnivå jämfört med den beteendemodellering som finns tillgänglig inom det hårdvarubeskrivande språket (HDL:en) när kompilatorn bestämmer tidpunkten för utbytet av data i den resulterande designen. Ericsson använder ett äldre gränssnitt för Advanced Peripheral Bus (APB) som kallas Memory/Register Interface (MIRI), vilket är ett gränssnitt för utbyte av data i ett delsystem i en av deras Application-Specific Integrated Circuit (ASIC:ar). Avhandlingen försöker uppgradera protokollet till ett av de det mer högpresterande ARM Advanced Microcontroller Bus Architecture – protokollen Advanced High-Performance Bus (AHB) eller Advanced eXtensible Interface (AXI). SystemC tillhandahåller en mängd funktioner för att definiera kretsens fullständiga beteende vid en hög abstraktionsnivå. Denna avhandling utforskar effekten av strukturerade SystemC-modeller och deras syntesresultat samt konstruktionsrymden, för att förstå den bästa designmetodiken i ett SystemC-modelleringsdesignflöde och jämföra modellerna baserade på de slutliga syntesmätvärdena som storlek, timing, etc. Verktygskedjan för avhandlingen kommer att vara Stratus HLS -kompilatorn som utvecklats av Cadence. Stratus stöder alla syntetiserbara konstruktioner av SystemC. HLS-forskningen fokuserar främst på att förbättra Design Space Exploration, dvs de algoritmer som används internt i HLS-verktygen för att komma fram till lösningar. För att ge HLS -motorerna en bättre utgångspunkt. I denna avhandling kommer Stratus att användas för att utvärdera olika modeller med ekvivalent beteende och nästan samma prestanda efter Syntes, för att komma fram till vilka konstruktioner är optimala för att den interna DSE-algoritmen skall fungera bäst.

A new design methodology that produces hardware solutions for performing real-time image processing is presented here. This design methodology provides significant advantages over traditional hardware design approaches by translating real-time image processing tasks into the gate-level resources of programmable logic-based hardware architectures. The use of programmable logic allows high-performance solutions to be realized with very efficient utilization of available logic and interconnection resources. These implementations provide comparable performance at a lower cost than other available programmable logic-based hardware architectures. This new design methodology is based on two components: a programmable logic-based destination hardware architecture and a suite of development system software. The destination hardware architecture is a Custom Computing Machine (CCM) that contains multiple Field Programmable Gate Array (FPGA) chips. FPGA chips provide gate-level programmability for the hardware architecture. Sophisticated software development tools, called the TRAVERSE development system software, are created to overcome the significant amount of time and expertise required to manually utilize this gate-level programmability. The new hardware architecture and development system software combine to establish a unique design methodology. There are several distinct contributions provided by this dissertation. The new flexible MORRPH hardware architecture provides a more efficient solution for creating real-time image processing computing machines than current commercial hardware architectures. The TRAVERSE development system software is the first integrated development system specifically for creating real-time image processing designs with multiple FPGA-based CCMs. New standards and design conventions are defined specifically for creating solutions to low-level image processing tasks, using the MORRPH architecture for verification. The circuit partitioning and global routing programs of the TRAVERSE development system software enable automated translation of image processing designs into the resources of multiple FPGA chips in the hardware architecture. In a broad sense, the individual contributions of this dissertation combine to create a new design methodology that will change the way hardware solutions are created for real-time image processing in the future. / Ph. D.

Thesis (MScEng)-- Stellenbosch University, 2013. / ENGLISH ABSTRACT: A wide variety of design methodologies exist in literature and the methodologies employed may differ among companies and even among design teams. Therefore a software tool, called DiDeas II, is being developed for the early phases of mechanical engineering design. DiDeas II is customisable to accommodate various design methodologies. An approach for customisability which allows the user interface and data structure to be customised without changing the source code has been implemented in previous developments via an approach combining ontology and conceptual graphs. This approach is expanded in this thesis to allow for the implementation of various design methodologies through the use of tables for the display of information with inheritance of data among these tables. During groupwork, communication is both asynchronous and synchronous. DiDeas II has been developed in this thesis to facilitate and capture both asynchronous and synchronous communication between team members. Capturing such communications has the potential to provide insight into design decisions. The communication functionality was assessed in case studies in an academic environment. DiDeas II proved to be effective at recording “soft” information during design and placing the information into context for future reference. The degree to which DiDeas II could be customised to suit the design process at different companies was assessed through discussions with engineers in industry. These discussions showed that it was possible to customise DiDeas II according to the design processes followed by the participants. / AFRIKAANSE OPSOMMING: „n Wye verskeidenheid ontwerpsmetodologieë bestaan in die literatuur en die metodologieë wat gebruik word kan tussen maatskappye en selfs tussen ontwerpspanne verskil. Daarom word „n sagteware-hulpmiddel, genaamd DiDeas II, ontwikkel vir die vroeë fases van meganiese ingenieursontwerp. DiDeas II is pasbaar om voorsiening te maak vir verskeie ontwerpsmetodologieë. „n Benadering vir pasbaarheid wat toelaat dat die gebruikerskoppelvlak en datastruktuur aangepas kan word sonder om veranderings aan die bron-kode te maak, is geïmplementeer in vorige ontwikkelings deur „n benadering wat ontologie en konseptuele grafieke kombineer. Hierdie benadering is in hierdie tesis uitgebrei om voorsiening te maak vir die implementering van verskeie ontwerpsmetodologieë d.m.v. tabelle vir die vertoon van informasie, met data wat “oorgeërf” word tussen hierdie tabelle. Kommunikasie is beide asinkroon en sinkroon tydens groepwerk. DiDeas II is in hierdie tesis verder ontwikkel om beide asinkrone en sinkrone kommunikasie metodes te bemiddel en daarvan rekord te hou. Die rekordhouding van sulke kommunikasie het die potensiaal om insig te bied aangaande ontwerpbesluite. Die kommunikasie funksionaliteit is geassesseer in gevallestudies in „n akademiese omgewing. DiDeas II was effektief in die rekordhouding van “sagte” informasie tydens ontwerp, sowel as om sulke informasie binne konteks te plaas vir latere verwysing. Die mate waartoe DiDeas II aangepas kan word om voorsiening te maak vir die ontwerpsprosesse van verskillende maatskappye, is geassesseer deur gesprekke met ingenieurs in industrie. Hierdie gesprekke het getoon dat dit moontlik is om DiDeas II aan te pas volgens die ontwerpsprosesse wat die deelnemers gebruik.

Biological organisms, phenomena and strategies, herein referred to as biological systems, provide a rich set of analogies that can be used to inspire engineering innovation. Biologically-inspired, or biomimetic, designs are publicly viewed as creative and novel solutions to human problems. Moreover, some biomimetic designs have become so commonplace that it is hard to image life without them (e.g. velcro, airplanes). Although the biologically- inspired solutions are innovative and useful, the majority of inspiration taken from nature has happened by chance observation, dedicated study of a specific biological entity (e.g., gecko), or asking a biologist to explain the biology in simple terms. This reveals a fundamental problem of working across the engineering and biological domains. The effort and time required to become a competent engineering designer creates significant obstacles to becoming sufficiently knowledgeable about biological systems (the converse can also be said). This research aims to remove the element of chance, reduce the amount of time and effort required to developing biologically-inspired solutions, and bridge the seemingly immense disconnect between the engineering and biological domains. To facilitate systematic biologically-inspired design, a design methodology that relies on a framework of tools and techniques that bridge the two domains is established. The design tools and techniques that comprise the framework achieve: Identification of relevant biological solutions based on function; translation of identified biological systems of interest; functional representation of biological information such that it can be used for engineering design activities; and conceptualization of biomimetic engineering designs. Using functional representation and abstraction to describe biological systems presents the natural designs in an engineering context and allows designers to make connections between biological and engineered systems. Thus, the biological information is accessible to engineering designers with varying biological knowledge, but a common understanding of engineering design methodologies. This work has demonstrated the feasibility of using systematic design for the discovery of innovative engineering designs without requiring expert-level knowledge, but rather broad knowledge of many fields. / Graduation date: 2011