Cette thèse porte sur les défis techniques et technologiques dans la conception des architectures mobiles d'émission « tout numérique » reconfigurables fonctionnant dans les bandes cellulaires pour les standards GSM, W-CDMA, HSUPA et LTE. Avec l'évolution constante des besoins en communication, les terminaux mobiles doivent être en mesure de couvrir différents standards à partir d'une même architecture, en fonction des bandes de fréquences libres, du débit et des contraintes spectrales. Dans un but de réduction des coûts, de consommation et d'une plus grande intégration, de nouvelles architectures dites multistandards se sont développées permettant à un seul émetteur d'adresser chaque standard au lieu de paralléliser plusieurs architectures radio chacune dédiée à un standard particulier. Depuis plusieurs années ont émergé des technologies nanométriques telles que le CMOS 90nm ou 65nm, ouvrant la voie à une plus grande numérisation des blocs fonctionnels des architectures jusqu'alors analogiques. Dans cette étude, nous identifions les évolutions possibles entre « monde analogique » et « monde numérique » permettant de déplacer la limite de la bande de base jusqu'à l'amplificateur de puissance. Plusieurs architectures ont été étudiées avec des degrés de numérisation progressifs jusqu'à atteindre l'architecture « tout numérique » englobant une partie de l'amplification de puissance. Un travail approfondi sur l'étude des différents standards cellulaires mené conjointement avec l'implémentation et la simulation de ces architectures, a permis d'identifier les différents verrous technologiques et fonctionnels dans le développement d'architectures « tout numérique ». Les contraintes de pollution spectrale des raies de sur-échantillonnage sont apparues comme dimensionnantes. Pour chaque bande de chaque standard, ces contraintes ont été évaluées, afin de définir une méthode d'optimisation des fréquences de sur-échantillonnage. Cependant un filtrage externe reste nécessaire. Une deuxième étape nous a amené à identifier et concevoir une technique de filtrage passe bande reconfigurable pour les bandes cellulaires de 1710 à 1980MHz avec au moins 60MHz de largeur de bande afin d'adresser le standard LTE, et 23dB d'atténuation à 390MHz du centre de la bande pour adresser le pire cas de filtrage (bandes 1, 3 et 10 en W-CDMA). Nous avons alors conçu et implémenté un filtre reconfigurable à inductances actives, afin de garantir reconfigurabilité et très faibles pertes d'insertion. Cette thèse a donc permis à partir d'une problématique actuelle et au travers d'une démarche d'identification des limites des architectures « tout numérique », de proposer un prototype de filtre adapté. Ce filtre a été conçu en CMOS 65nm, réalisé et mesuré, les performances sont conformes aux exigences requises / This thesis addresses the technical and technological challenges in the design of “all digital” reconfigurable mobile architectures operating cellular standard bands (GSM, WCDMA, HSUPA and LTE). With the ever-changing communication needs, mobile devices must be able to address different standards from a common architecture depending on free frequency bands, data rate and spectral constraints. In order to reduce costs, consumption and to obtain a greater integration, new architectures were developed and called multi-standard allowing a single transmitter to transmit each standard instead of parallelizing several radio architectures each dedicated to a particular standard. For several years nanoscale technologies such as 90nm or 65nm CMOS have emerged, clearing the way to replace analog functional blocks by greater digital functional blocks. In this study, we identify possible changes between "analog world" and "digital world" to move the digital boundary from the baseband to power amplifier. Several architectures have been studied with progressive digitization degrees to meet "all digital" architecture, comprising part of the power amplifier. Extensive work on the study of different cellular standards conducted jointly with the implementation and simulation of these architectures, let us identified the different technological and functional locks in the development of "all digital" architectures. Oversampling spurious constraints have emerged as dimensioning. For each band of each standard, these constraints were evaluated to define an optimization method of over-sampling frequency. However an external filter is required. A second step led us to identify and design a reconfigurable bandpass filtering technique for cellular bands from 1710 to 1980MHz with at least 60MHz of bandwidth in order to address the LTE, and 23dB attenuation at 390MHz from the center of the filter to address the most constringent filtering cases (bands 1, 3 and 10 in W-CDMA). We then designed and implemented a reconfigurable filter based on active inductors to ensure reconfigurability and very low insertion loss. This thesis permit from an actual architecture system issue and through a process to identify limitations of “all digital” architectures, to propose an adapted filtering solution. This filter was designed in 65nm CMOS, implemented. Measured performance is consistent with requirements

Orientador: Prof. Dr. Carlos Eduardo Capovilla / Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-Graduação em Engenharia Elétrica, 2015. / Este trabalho tem como escopo o projeto e implementação de indutores ativos integrados em tecnologia CMOS para operação em circuitos integrados de r'adio frequência. Tais sistemas demandam por indutores passivos integrados, sendo que estes geralmente apresentam baixa indutância, baixo fator de qualidade, e tamanhos relativamente grandes. Estes fatores são limitantes no projeto de circuitos integrados. Como alternativa, indutores ativos integrados têm sido propostos, com o uso de circuitos que emulam o efeito do indutor passivo convencional. Estes circuitos apresentam menor dimens¿ao, possibilidade de ajustes no valor da indut¿ancia, da frequ¿encia de opera¸c¿ao, do fator de qualidade, ao custo de consumo de pot¿encia DC e um relativo aumento no ru'ýdo total do sistema. Al'em de um profundo estudo, quatro topologias distintas de indutores ativos integrados foram abordadas e projetadas, em seguida foi projetado um VCO aplicando dois indutores ativos como ressonadores. Uma an'alise a n'ývel de projeto utilizando a t'ecnica de-embedding 'e aplicada no projeto de um indutor ativo. Os modelos dos componentes utilizados s¿ao baseados na biblioteca CMOS em alta frequ¿encia da foundry austr'ýaca AMS. / This study aimed to design and implement integrated active inductors in CMOS technology for operation in integrated radio frequency circuits. These systems demand for integrated passive inductors, and these usually have low inductance, low quality factor, and relatively large sizes. These factors are limiting in integrated circuit design. As an alternative integrated active inductors have been proposed, with the use of circuits that emulate the effect of conventional passive inductor. These circuits have smaller, the possibility for tuning the inductance value, the operation frequency, quality factor, at the cost of DC power consumption and a relative increase in total system noise. In addition to a thorough study, four different topologies ofintegrated active inductors were approached and designed, then was design a VCO applying two active inductors as resonators. An examination at the design level using the de-embedding technique is applied in the design of an active inductor. The models of the components used are based on CMOS library at high frequency of the Austrian foundry AMS.

Orientador: Prof. Dr. Carlos Eduardo Capovilla / Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-Graduação em Engenharia Elétrica, 2017.

Orientador: Luiz Carlos Kretly / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-09T03:22:24Z (GMT). No. of bitstreams: 1 Silva_Eduardo_M.pdf: 14948633 bytes, checksum: 63579d1a8844e33a2c577a9aed963b41 (MD5) Previous issue date: 2007 / Resumo: Este trabalho tem como escopo o projeto e implementação de indutores ativos em tecnologia CMOS para operação em sistemas de rádio freqüência. A grande área demandada por indutores passivos integrados, bem como a sua baixa indutância e baixo fator de qualidade associados, apresentam-se como um dos maiores limitantes no projeto de circuitos integrados aplicados às comunicações. Como alternativa, indutores ativos integrados têm sido propostos. O uso de topologias de circuitos que emulam o efeito do indutor passivo convencional torna-se atraente ao passo que o grau de compactação e seletividade podem ser obtidos. Quatro topologias distintas de indutores ativos integrados são abordadas, bem como uma aplicação prática. Resultados de simulação e de experimentos são apresentados / Abstract: This work aims the design and implementation of integrated active inductors in CMOS technology for applications in radio frequency systems. The large area occupied by passive inductors, as well its low quality factor and low inductance, have been detached as one of the major drawbacks in the design of integrated circuits applied to communication systems. Alternately, active inductors have been proposed. Circuits usage which emulates conventional spiral inductors becomes interesting since die area reduction and selectivity can be obtained. Four different topologies of integrated active inductors are discussed, as well a practical application. Simulation results and experimental results are presented. / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

No description available.

With the increase in demand for compact and high data rate communication systems, there is a need for high efficiency with modulated signals (PAPR 5-10 dB) for base-station power amplifiers. One of the famous architectures used to achieve this is Doherty architecture. The architecture has recently been extended to the Load Modulated Balanced Amplifier (LMBA) concept, where a separate integrated amplifier generates the control signal for load modulation. Almost all published studies are concerned with discrete "PCB-based" solutions for LMBA. In a recent study [1], the potential of designing an integrated LMBA in 0.18 μm CMOS has been evaluated. The main limitation concerning losses and area comes from the quadrature couplers, consisting of either two or four inductors. Using active inductors in the coupler design may be possible to obtain a more cost-effective solution. However, several aspects must be taken into consideration. One is that the power consumption of the active inductor should not exceed the power loss of the passive inductor. Another one is the ability to handle high power signals (high voltage swing), corresponding to 10-15 dBm at the input of the amplifier. The main objective of this thesis is to implement a hybrid coupler using an active inductor based on the theory of gyrators. The circuits were implemented using TSMC 0.18 μm process. The coupler and the active inductor are designed to operate at 2 GHz centre frequency. The active inductor implemented is considerably linear up to 12 dBm. The coupler has an input reflection coefficient (S11) of -26 dB, the transmission coefficient (S21) of -4.4 dB, and a coupling coefficient (S31) of -2.4 dB. The coupler shows good coupling and isolation characteristics. The phase difference between the through-port and the coupled-port of the coupler is 92°. As a result, when used as a power divider at the input of the power amplifiers, a PAE (Power Added Efficiency) of 63% and output power of 23 dBm is obtained at an input power of 12 dBm.

No description available.

Inductors are extensively used in the design of radio-frequency circuits. In the last decade, the integration of passive components, especially inductors on silicon chips, has led to the widespread development and implementation of Radio Frequency Integrated Circuits (RFICs) in CMOS technologies. However, on-chip passive inductors occupy a large silicon chip area and hardly scale down with technology scaling. Therefore, on-chip passive inductors become formidable obstacles to the realization of highly dense RFICs to be integrated with other highly dense digital circuits on a single chip using a common fabrication process. In recent years, researchers have focused on replacing passive inductors with transistor-only active circuits, namely active inductors. Active inductors can be realized with only a few transistors, which scale down with technology scaling. Therefore, they occupy a fraction of the chip area of their passive counterparts, and can be implemented densely in CMOS processes. Unlike passive inductors, bias dependent operations of active inductors allow for the tuning of their inductance and quality factor Q, and in turn, tuning the performance parameters of RFICs. This thesis focuses on the design and development of passive inductorless CMOS RFICs for ultra-wideband (UWB) receiver front-ends using active inductors. A new Q-enhanced and a new bandwidth-extended tunable active inductors are designed. Using the Q-enhanced active inductor, two tunable UWB low-noise amplifiers (LNAs) (two-stage and three-stage UWB LNAs), a UWB mixer and a wideband local-oscillator (LO) driver are designed. Active inductors are utilized to develop a novel wideband active shunt-peaking technique that decreases high-frequency losses to yield a flat gain over a wide bandwidth. A tunable multiband-UWB front-end integrating a two-stage UWB LNA, and a pair of UWB mixers driven by a pair of wideband LO drivers, is fabricated in a 90nm digital CMOS process. The passive inductorless two-stage UWB LNA, three-stage UWB LNA and UWB front-end occupy chip areas of only 0.0114mm2, 0.0227mm2, and 0.1485mm2, respectively. The active CMOS UWB front-end exhibits a measured flat gain of 22.5dB over 2.5-8.8 GHz bandwidth, and its tunability allows for varying the gain and bandwidth. / Integrated Circuits and Systems

No description available.

No description available.