Im Rahmen der Gemeinsamen Agrarpolitik der Europäischen Union wurden Agrarumweltprogramme (AES) entwickelt, um die durch die Landwirtschaft verursachte Zerstörung der natürlichen Umwelt zu bekämpfen. Um die ökologische Wirksamkeit der Systeme zu verbessern, wird ein kollektiver Ansatz empfohlen, der sich auf eine Landschaft statt auf eine einzelne Betriebsebene konzentriert. Dieser Ansatz wird in ganz Europa selten angewendet, außer in den Niederlanden, wo seit 2016 alle AES gemeinsam realisiert werden müssen. Da die Teilnahme an den Programmen freiwillig ist, ist es von entscheidender Bedeutung, die Motivation der Landwirte zu verstehen, sich anzuschließen, da die Annahme und Umsetzung von Maßnahmen eine Voraussetzung für die Erreichung ist irgendwelche Effekte. Ziel dieser Studie ist es daher, die Motivation niederländischer Landwirte zur Teilnahme an kollektiven AES zu untersuchen und die wichtigsten Vor- und Nachteile des Programms herauszufinden, die von den Landwirten wahrgenommen werden. Eine Q-Studie mit 15 Landwirten aus sechs Provinzen zeigt drei vorherrschende Motivationsansichten: eine kollektivorientierte, eine wirtschaftsorientierte und eine umweltorientierte Perspektive. Alle Bauern eint ihre Zuneigung und Sorge für die Natur, die von unterschiedlichem Problembewusstsein und Kollektivzugehörigkeit begleitet wird. Finanzieller Ausgleich wird von allen als wichtig erachtet, jedoch eher als notwendiges Mittel, um notwendige Änderungen in der landwirtschaftlichen Praxis zu ermöglichen, denn als zusätzliche Einnahmequelle. Während die niederländischen Regelungen noch weiter verbessert werden können, um mehr Flexibilität, eine bessere Integration des Wissens der Landwirte und eine bessere Kommunikation zu ermöglichen, weisen alle Landwirte viele Vorbehalte im Zusammenhang mit kollektiven Maßnahmen zurück, was darauf hindeutet, dass der niederländische Ansatz über die nationalen Grenzen hinaus gefördert werden könnte. / Within the European Union’s Common Agricultural Policy, agri-environment schemes (AES) have been designed to address the degradation of the natural environment caused by agriculture. To improve the schemes’ ecological effectiveness, a collective approach focusing on a landscape instead of a single farm level is recommended. This approach is rarely applied across Europe except for the Netherlands, where all AES have to be realised collectively since 2016. As participation in the schemes is voluntary, understanding farmers’ motivation to join is crucial since the uptake and implementation of measures is prerequisite for achieving any effects. Hence, the aim of this study is to explore Dutch farmers’ motivation to participate in collective AES and to find out about the scheme’s main advantages and disadvantages perceived by the farmers. A Q study with 15 farmers from six provinces shows three dominant motivational views: a collective-oriented, a business-oriented and an environment-oriented perspective. All farmers unites their affection and care for nature, which is accompanied by different levels of problem awareness and affiliation to the collective. Financial compensation is deemed important by all, yet rather as necessary mean to enable required changes in farming practices than as additional source of revenue. While the Dutch schemes can still be further improved to allow for more flexibility, a better integration of the farmers’ knowledge and enhanced communication, all farmers dismiss many caveats related to collective action, indicating a potential to promote the Dutch approach beyond national borders.

With the upcoming 5G networks and expected growth of the Internet of Things (IoT), the demand for fast and reliable encryption algorithms will increase. As many systems might be time critical and run on internal power sources, the algorithms must be small, fast, energy efficient and have low latency. A new stream cipher called Espresso has been proposed to answer these demands, optimizing for several parameters unlike other stream ciphers such as Trivium and Grain. Espresso has previously been compared to the industry standard, Advanced Encryption Standard (AES), in a FPGA implementation and has shown promising results in terms of power usage but further testing needs to be done to gain knowledge about the ciphers characteristics. The purpose of this thesis is to implement and evaluate Espresso in 65nm CMOS technology and compare it to AES. Espresso is implemented in VHDL in several configurations, optimizing for size and latency. The implementations are then compared to AES is in terms of area, throughput, energy efficiency and latency through simulation. This is done using the UMC 65nm CMOS library and Synopsys Design Vision. It is found that Espresso, implemented with 1 bit sequential loading of the key and IV, is 18.2x smaller, 3.2x faster, uses 9.4x less power and has 1.5x less latency than AES. When implemented with full parallel loading, Espresso still is 13.6x smaller, 3.2x faster, draws 7.1x less power while also having 3.2x lower latency than AES. Espressos energy efficiency can further be improved by applying low- power techniques although some techniques, like clock gating and power gating, have limited applicability due to of the nature of stream ciphers. / Med de kommande 5G nätverken och den förväntade tillväxten av Internet of Things (IoT) kommer efterfrågan på snabba och pålitliga krypteringsalgoritmer att öka. Eftersom många system kan vara tidskritiska och drivas av interna kraftkällor måste algoritmerna vara små, snabba, energieffektiva och ha låg latens. Ett nytt strömchiffer vid namn Espresso har föreslagits som ett svar på dessa krav och har optimiserats för flera parametrar till skillnad från andra strömchiffer såsom Trivium och Grain. Espresso har tidigare jämförts med branschstandarden, Advanced Encryption Standard (AES), i en FPGA implementation och visat lovande resultat för strömförbrukning men ytterligare tester måste utföras för att få kunskap om algoritmens egenskaper. Syftet med detta examensarbete är att implementera och utvärdera Espresso i 65nm CMOS teknologi och jämföra den med AES. Espresso implementeras i flera konfigurationer i VHDL som optimiserar för storlek och latens. Implementationerna jämförs sedan med AES i area, genomströmning, energieffektivitet och latens genom simulering. Detta görs med hjälp av UMC 65nm CMOS biblioteket och Synopsys Design Vision. Resultaten visar att Espresso implementerad med sekventiell laddning av nyckel och IV är 18.2x mindre, 3.2x snabbare, använder 9.4x mindre ström och har 1.5x mindre latens än AES. När Espresso implementeras med full parallel laddning är den fortfarande 13.6x mindre, 3.2x snabbare, drar 7.1x mindre ström men har samtidigt 3.2x lägre latens än AES. Espresso’s energieffektivitet kan förbättras ytterligare genom att applicera strömsparande tekniker, även om vissa tekniker såsom clock gating och power gating har begränsad användbarhet på grund av strömchiffers natur.

Sammanfattning Bakgrund - Dagens processorer börjar närma sig gränsen för hur höga klockfrekvenser de kan köras i. Detta har lett till att processorer har fått fler kärnor för att kunna exekvera flera processer parallellt med flertrådade applikationer. Det finns dock ofta en stor mängd oanvänd beräkningskraft under långa perioder då datorn är igång som ligger i grafikprocessorn, GPU. Då en GPU kan köra tusentals många fler trådar på samma gång än en CPU har ramverk för att göra mer generella beräkningar på GPU utvecklats, dessa kallas för GPGPU-ramverk. Då varje kärna på en GPU inte är lika stark som på en CPU ligger vinsten i att använda algoritmer som går bra att parallellisera. En sådan algoritm är krypteringsalgoritmen AES som är en av de säkraste och vanligaste krypteringsalgoritmerna som används idag. Syfte – Med hjälp av GPU-accelerering kan man kryptera med AES snabbare än med en traditionell CPU-lösning. För att göra GPU-accelereringen så effektiv som möjligt undersöker detta examensarbete vilken AES-metod samt vilket GPGPU-ramverk man bör välja. Metod – För att undersöka vilken/vilka AES-metoder samt vilka GPGPU-ramverk som var lämpliga att använda för denna undersökning gjordes två litteraturstudier. Utifrån data som litteraturstudierna gav genomfördes experiment för att jämföra de valda GPGPU-ramverken med den valda AES-metoden som ansågs vara mest lämpliga. Resultat – Från litteraturstudierna kom det fram att OpenCL och CUDA blir de rekommenderade GPGPU-ramverken och att CTR blir den rekommenderade AES-metoden för AES-kryptering med GPGPU-programmering. Utifrån experimenten som genomförts kunde det konstateras att CUDA är ett effektivare GPGPU-ramverk än OpenCL för AES-CTR på det testade grafikkortet, GTX 560. Implikationer – CUDA är snabbare vid större filer för att OpenCL begränsas mer av dataöverföringshastigheten än CUDA på ett GTX 560. Begränsningar – Experimenten genomfördes endast på ett grafikkort från Nvidia. Eftersom Nvidia inte har något intresse i att optimera för andra GPGPU-ramverk så kunde inte testresultaten från OpenCL verifieras med externa verktyg. Detta p.g.a. att Nvidias verktyg inte längre stödjer debugging eller profiling för OpenCL. Nyckelord – Processorer, GPGPU, AES, CTR, OpenCL, CUDA, GPGPU-ramverk / Abstract Background - Processors today are approaching the limit for how high clockfrequences they can run. This has led to that instead of trying to make them run faster they are instead made with multiple cores so they can utilize parallelization by running several threads in parallel. However aside from the CPU there is still the graphics card which has a large amount of unused computing power for long durations of time while the computer is active. While a GPU might not have as quick processors it instead has several thousands of them at the same time than a CPU which have led to the development of GPGPU-frameworks to use that potential parallelization. The profit in this lies in using algorithms and code functions that got high potential parallelization, one of which is the AES encryption algorithm. AES is one of the most widely used encryption algorithms today and also considered to be one of the most secure. Purpose – By using GPGPU-acceleration the encryption speed of AES is higher than by using a traditional CPU approach. To make the GPU-acceleration as effective as possible this study looks into which AES-method and which GPGPU-framework that should be chosen during development. Method – This study makes two literature studies to determine which AES-methods and which GPGPU-frameworks that are viable for GPU-acceleration of AES. Afterwards this study conducts experiments to determine which of these GPGPU-frameworks are the most effective. Findings – The conclusion drawn from the literature study is that the CTR-method among the AES-methods is preferable due to its parallelization potential and high security measures. Among the current GPGPU-frameworks only two frameworks satisfies the criteria determined from the literature study and those are CUDA and OpenCL. From the experiment the conclusion is thereafter drawn that of the two GPGPU-frameworks CUDA is more effective due to the bandwidth limits that OpenCL have compared to CUDA. This conclusion is valid on at least the tested graphics card, GTX 560. Implications – CUDA is faster at larger file sizes than OpenCL due to limited data transfer speed in OpenCL on a GTX 560. Limitations – The experiments were only conducted on one graphics card from Nvidia due to hardware constraints in that CUDA can only be run on Nvidia hardware. Due to this hardware constraint and Nvidia’s lack of support in their tools for debugging and profiling of OpenCL the results from the testing of OpenCL couldn’t be verified using external tools. Keywords – Processor, GPGPU, AES, CTR, OpenCL, CUDA, GPGPU-framework

Anion-exchange chromatography with inductively coupled plasma - atomic emission spectrometry (ICP-AES) has been used for the speciation of chromium (Cr). Chromium speciation has attracted attention because of the different toxicity, Cr(III) is relatively non-toxic and Cr(VI) has been classified as a human carcinogen. The aim of the present study was to develop simple method for the speciation analysis of Cr (Cr(III) and Cr(VI)) in particulate matter of urban dust. A combination of 2% KOH + 3% Na2CO3 has been chosen as the optimal reagent for the extraction of chromium from particular matter. It was found that there was no conversion of Cr(VI) into Cr(III). The effect of separation parameters such as acidity of mobile phase was also studied. The detection limit for Cr(VI) was about 12 ng.ml-1 . Results for the determination of Cr(VI) were confirmed by the analysis of standard reference material (BCR CRM 545, Cr(VI) in welding dust loaded on a filter) with good agreement between certified (40,16 ± 0,60 μg.g-1 ) and found (37,83 ± 1,14 μg.g-1 ) values.

As of 21st September 2017, industrial use of hexavalent chromium (Cr(VI)) will, due to its environmental toxicity and carcinogenicity, be restricted by REACH regulations. Saab Aeronautics is therefore shifting anticorrosion surface treatment of aluminum alloys from hexavalent chromium conversion to trivalent chromium (Cr(III)) passivation. The purpose of this thesis is to investigate the characteristics of conversion coatings formed with the passivation chemical SurTec 650V, in order to facilitate transfer to the more environmental friendly alternative. Process parameters, such as pH and immersion time in SurTec 650V passivation baths, have been investigated for passivation of three different aluminum alloys; 2024, 6061 and 7075. The characteristics of the Cr(III) conversion coatings achieved at laboratory scale in the thesis work have been compared with SurTec 650V process in production scale and with Cr(VI) containing Alodine 1200 and Alodine 1500 processes. The impact of varying process parameters have been investigated with goniometry, x-ray photoelectron spectroscopy (XPS), auger electron spectroscopy (AES), scanning electron microscopy (SEM) and transmission electron microscopy (TEM) to analyse characteristics of the conversion coatings. Differences in chemical composition on the surface and in depth profile was detected with XPS and AES, respectively and topology of coatings was found to differ for different aluminium alloys and parameter combinations. With TEM, the thickness of the conversion coating was found to be approximately 30-50 nm, which is thinner than the coatings formed with Cr(VI) passivation. Characteristics of coatings formed with Cr(III) passivation is concluded to be very dependent on parameter variation, especially for alloy 2024. Differences also occur between passivation at laboratory and production scale. Further evaluation of the production scale SurTec 650V process and corrosion testing should be performed, and an elaboration of a process control is required before the shift to an environmental friendly passivation process can be completely successful at Saab.

IoT devices are   increasingly used in the process of gathering scientific data. In   environmental monitoring IoT devices can be used as remote sensing devices to   collect information about e.g. temperature. To keep data reliable, various   security aspects have to be considered. Constrained devices are limited by   memory size and battery life, a security solution has to be developed with   this in mind. In this study an IoT security solution was developed in collaboration   with a research group in environmental science at Umeå University. We   selected commonly used algorithms and compared them with the goal to provide   authentication and integrity for an IoT application, while minimizing energy   use running on an Atmega 1284P. The results showed that the encryption   algorithm AES-256-GCM is a good choice for a total security solution.   AES-256-GCM provides authenticated encryption with additional data while, in   relation to the other tested algorithms, using energy at a low level and   leaving a small program size footprint.

CICYT (PB88-0288 y PTRI91-0029)

No description available.

The resources required to have humans score extended written response items in English language learner (ELL) contexts has caused automated essay scoring (AES) to emerge as a desired alternative. However, these systems often rely heavily on indirect proxies of writing quality such as word, sentence, and essay lengths because of their strong correlation to scores (Vajjala, 2017). This has led to concern about the validity of the features used to establish the predictive accuracy of AES systems (Attali, 2007; Weigle, 2013). Reliance on construct-irrelevant features in ELL contexts also forfeits the opportunity to provide meaningful diagnostic feedback to test-takers or provide the second language acquisition (SLA) field with real insights (C.-F. E. Chen & Cheng, 2008). This thesis seeks to improve the validity and reliability of an AES system developed for ELL essays by employing a new set of features based on the acquisition order of English negation. Modest improvements were made to a baseline AES system's accuracy, showing the possibility and importance of engineering features relevant to the construct being assessed in ELL essays. In addition to these findings, a novel ordering of the sequence of English negation acquisition not previously described in SLA research emerged.

The increasing application of cryptographic algorithms to ensure secure communications across virtual networks has led to an ever-growing demand for high performance hardware implementations of the encryption/decryption methods. The inevitable inclusion of the cryptographic algorithms in network communications has led to the development of several encryption standards, one of the prominent ones among which, is the Rijndael, the Advanced Encryption Standard. Rijndael was chosen as the Advanced Encryption Standard (AES) by the National Institute of Standard and Technology (NIST), in October 2000, as a replacement for the Data Encryption Standard (DES). This thesis presents the architecture for the VLSI implementation of the Rijndael, the Advanced Encryption Standard algorithm. Rijndael is an iterated, symmetric block cipher with a variable key length and block length. The block length is fixed at 128 bits by the AES standard [4]. The key length can be designed for 128,192 or 256 bits. The VLSI implementation, presented in this thesis, is based on a feed-back logic and allows a key length specification of 128-bits. The present architecture is implemented in the Electronic Code Book(ECB) mode of operation. The proposed architecture is further optimized for area through resource-sharing between the encryption and decryption modules. The architecture includes a Key-Scheduler module for the forward-key and reverse-key scheduling during encryption and decryption respectively. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the Key-Scheduler module by expanding the initial secret key. The proposed architecture is designed using the Custom-Design Layout methodology with the Cadence Virtuoso tools and tested using the Avanti Hspice and the Nanosim CAD tools. Successful implementation of the algorithm using iterativearchitecture resulted in a throughput of 232 Mbits/sec on a 0.35[mu] CMOS technology. Using 0.35[mu] CMOS technology, implementation of the algorithm using pipelining architecture resulted in a throughput of 1.83 Gbits/sec. The performance of this implementation is compared with similar architectures reported in the literature.