<p>Virtually all satellite repeaters use a traveling-wave tube (TWT) as their main power amplifier. Because on-board power is a limited commodity, it is highly desirable that the TWT be operated as efficiently as possible, namely in or near saturation where it is highly nonlinear. These nonlinear effects manifest themselves as an amplitude compression (AM/AM conversion) effect and an amplitude dependent phase modulation (AM/PM conversion) effect. In this thesis a number of investigations have been made in relation to the TWT nonlinearities and their effect on the performance of communication systems.</p> <p>A novel quadrature model of the TWT has been developed. This model is most useful in that it is analytic and requires the choice of only four parameters to obtain an excellent fit to the TWT characteristics.</p> <p>An optimal bandpass nonlinear transfer characteristic that maximizes its output signal to interference power ratio has also been derived. By making use of this optimal transfer characteristic and the quadrature model of the tube, a computer-aided design procedure has been described for obtaining a predistortion compensation network for the TWT. This network consists of a simple arrangement of attenuators and power-law devices and has been shown, by computer simulation, to yield about 1 dB improvement in system performance for the case when only a single carrier is present in the TWT.</p> <p>In the case when a single sample detection and majority logic decision circuit is assumed at the receiver, it has been possible to derive analytical expression for the probability of error of M-ary CPSK signals transmitted through a piecewise-linear envelope limiting repeater. An infinite series expression for the bit error rate of binary CPSK transmission through an actual TWT channel has also been derived.</p> <p>A performance analysis of a correlation receiver with a linear integrate and dump circuit has been carried out for the case of binary CPSK transmission through a bandpass nonlinearity exhibiting AM/PM conversion.</p> <p>For the case of purely amplitude-limiting channels, an optimal (maximum-likelihood) receiver structure and its approximate performance has also been investigated.</p> / Thesis / Doctor of Philosophy (PhD)

A limiting factor in the widespread deployment of LMDS systems is the limited distance of current systems. Rain attenuation and limited transmitter power are the primary causes of the limited distance. Adaptive digital predistortion is presented as a method of increasing effective transmitter power. A background on LMDS link design, non-linear amplification, and predistortion is presented to assist the reader. A developed simulation uses AM-AM and AM-PM characteristics obtained from laboratory measurements of a 28 GHz amplifier to determine the effect of several predistortion implementation options and to confirm the feasibility of the proposed architecture. The potential impact of this predistortion architecture on LMDS system design is considered. The presented multi-stage predistortion architecture is found to be capable of implementation at Msymbol/second rates utilizing a FPGA or custom IC and a moderate speed digital signal processor. / Master of Science

L'objectif de cette thèse est de démontrer la faisabilité d'oscillateurs contrôlés en tension (O.C.T.) rivalisant en termes de bruit de phase avec les O.C.T. fabriqués en technologies III V. Cet O.C.T. doit être complètement intégré, adresser la bande Ku et utiliser la technologie QUBiC4X de NXP Semiconductors. Les travaux de cette thèse sont articulés autour de trois chapitres principaux, le premier revient sur les bases fondamentales à la compréhension des phénomènes inhérents aux composants électroniques et présents dans les oscillateurs plus particulièrement. Le second explique, en s'appuyant sur l'analyse des formes d'ondes et sur des calculs analytiques, les choix retenus en termes d'architecture pour la partie active ainsi que pour le résonateur afin de minimiser la conversion du bruit AM/PM et atteindre les meilleures performances possibles en bruit de phase. Il décrit les quatre versions d'O.C.T. réalisés et analyse les résultats de simulations post-layout obtenus pour justifier leur fabrication. Il présente notamment une architecture innovante utilisant les avantages d'un montage cascode ainsi qu'un résonateur à trois inductances différentielles imbriquées les unes dans les autres. Le troisième chapitre détaille les choix de design faits lors du dessin des masques ainsi que les résultats de mesures obtenus pour les quatre versions fabriquées. Enfin, il se termine par une énumération des recherches menées dans le but d'expliquer les différences observées entre les résultats de mesure et de simulation. / The thesis goal is to demonstrate the feasibility of voltage controlled oscillator (VCO) challenging the VCOs using III-V technologies regarding phase noise performances. This VCO must be fully integrated, target the Ku-band and use the QUBiC4X process from NXP Semiconductors. This thesis work is based on three main chapters, the first one reviews the fundamentals to understand the intrinsic phenomena in electronics components and more particularly in oscillators. The second explains, by using the waveforms analysis and analytical demonstrations, the choices made regarding both the active part and the resonator architecture in order to minimize the AM/PM noise conversion and then to reach the best phase noise performances. It describes the four versions of the realized VCOs and analyzes the post-layout simulations results to justify their fabrications. It shows more specifically an innovative architecture using the advantages of a cascode configuration and a resonator based on three interlocked differential inductors. Finally, the third chapter focuses on the masks' layout and measurements results of the four VCOs. It also details the investigations made to explain the differences between measurements and simulations.

The existing UHF Satellite Communications (SATCOM) transponders used for military applications use efficient, saturated power amplifiers, which provide one earth-coverage antenna beam. The amplifier is dedicated to small frequency band and only handles a few carriers simultaneously. The communications capacity needed to support future military forces on the move will require satellite payload power amplifiers to support hundreds of channels simultaneously, with the channels spread over the entire military UHF SATCOM band. To meet the capacity requirements and simultaneously meet the out-of-band emission, power amplifiers will have to be highly linear. The high-efficiency, ultra-linear power amplifier architecture proposed to support the requirements can only be met by use of linearity improvement techniques. The literature search revealed many power amplifier linearity improvement techniques. Each technique was reviewed to determine its suitability for the proposed power amplifier architecture. The adaptive digital predistortion technique was found to be the most suitable in terms of bandwidth, correction achievable, and complication. A discussion on common linearization techniques is presented, followed by analysis of the adaptive digital predistortion technique. A SIMULINK simulation model of an adaptive digital predistorter was developed. The simulation results show that adaptive digital predistortion was able to significantly reduce the Inter-Modulation Distortion (IMD) terms generated by a memory-less power amplifier operating in the 240 MHz to 270 MHz range. An actual hardware implementation of adaptive digital predistorter was constructed and the test results show that there was a large reduction in IMD terms generated by a memory-less power amplifier. In the contrary, the results show there is only moderate improvement in IMD performance if the power amplifier has memory. The electrical memory in the power amplifier with memory was minimized, but this resulted only a modest improvement in the IMD performance. Therefore, it was concluded the majority of the memory effect was due to thermal memory.

The recent trend in modern information technology has been towards the increased use of portable and handheld devices such as cellular telephones, personal digital assistants (PDAs), and wireless networks. This trend presents the need for compact and power efficient radio systems. Typically, the most power inefficient device in a radio system is the power amplifier (PA). PA inefficiency requires increased battery reserves to supply the necessary DC bias current, resulting in larger devices. Alternatively, the length of time between battery charges is reduced for a given battery size, reducing mobility. In addition, communications channels are becoming increasingly crowded, which presents the need for improved bandwidth efficiency. In order to make more efficient use of the frequency spectrum allocated for a particular system, there is a push towards complex higher order digital modulation schemes in modern radio systems, resulting in stricter linearity requirements on the system. Since power efficient amplifiers are typically nonlinear, this poses a major problem in realizing a bandwidth and power efficient radio system. However, by employing various linearization techniques, the linearity of a high efficiency PA may be improved. The work presented in this thesis focuses on diode predistortion linearization, particularly for PA RFICs in digital radios. Background discussion on common linearization techniques available to the PA designer is presented. In addition, a discussion of traditional and modern methods of nonlinearity characterization is presented, illustrating the nonlinear PA effects on a modulated signal. This includes the use of two-tone analysis and the more modern envelope analysis. The operation of diode predistortion linearizers is discussed in detail, along with diode optimization procedures for PA linearization with minimum impact on return loss and gain. This diode optimization is effective in improving the ability to integrate the predistorter into a single, linearized PA RFIC chip. MESFET and HBT based diode linearizers are studied for use with corresponding MESFET and HBT based PAs in the 2.68 GHz and 1.95 GHz frequency bands, respectively. Results show an improvement in adjacent channel power ratio (ACPR) due to the linearizer in both MESFET and HBT cases. A fully integrated 1.95 GHz linearizer and PA RFIC in HBT technology is also presented. Design considerations, simulations, and layouts for this design are presented. Finally, several recommendations are made for continued research in this area. / Master of Science

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Aerospace Report No. TOR-0059(6110-01)-3, section 1.3.3 outlines the design and performance requirements of SGLS (Space Ground Link Subsystem) uplink services equipment. This modulation system finds application in the U.S. Air Force satellite uplink commanding system. The SGLS signal generator is specified as an FSK (Frequency Shift Keyed)/AM (Amplitude Modulation)/PM (Phase Modulation) sub-carrier modulator. GDP Space Systems has implemented, on a single 6U-VME card, a SGLS signal generator. The modulator accepts data from several possible sources and uses the data to key one of three FSK tone frequencies. This ternary FSK signal is amplitude modulated by a synchronized triangle wave running at one half the data rate. The FSK/AM signal is then used to phase modulate a tunable HF (High-Frequency) sub-carrier. A digital design approach and the availability of integrated circuits with a high level of functionality enabled the realization of a SGLS signal generator on a single VME card. An analog implementation would have required up to three rack-mounted units to generate the same signal. The digital design improve performance, economy and reliability over analog approaches. This paper describes the advantages of a digital FSK/AM/PM modulation method, as well as DDS (Direct Digital Synthesis) and digital phase-lock techniques.

<div>Radio Frequency Power Amplifiers (PA) are essential components of wireless systems and nonlinear in a permanent way. So, high efficiency and linearity at a time are imperative for power amplifiers. However, it is hard to obtain because high efficiency Power Amplifiers are nonlinear and linear Power Amplifiers have poor efficiency. To meet both linearity and efficiency, the linearization techniques such as Digital Predistortion (DPD) has arrested the most attention in industrial and academic sectors due to provide a compromising data between efficiency and linearity. This thesis proposed on digital predistortion techniques to control nonlinear distortion in radio frequency transmitters. </div><div>By using predistortion technique, both linearity and efficiency can obtain. In this thesis a new generic Saleh model for use in memoryless nonlinear power amplifier (PA) behavioral modelling is used. The results are obtained by simulations through MATLAB and experiments. We explore the baseband 13.56 MHz Power Amplifier input and output relationships and reveal that they apparent differently when the Power Amplifier shows long-term, short-term or memory less effects. We derive a SIMULINK based static DPD design depend on a memory polynomial. A polynomial improves both the non-linearity and memory effects in the Power Amplifier. As PA characteristics differs from time to time and operating conditions, we developed a model to calculate the effectiveness of DPD. We extended our static DPD design model into an adaptive DPD test bench using Indirect Learning Architecture (ILA) to implement adaptive DPD which composed of DPD subsystem and DPD coefficient calculation. By this technique, the output of PA achieves linear, amplitude and phase distortions are eliminated, and spectral regrowth is prevented. </div><div>The advanced linearity performance executed through the strategies and methods evolved on this thesis can allow a higher usage of the capability overall performance of existing and emerging exceptionally performance PAs, and therefore an anticipated to have an effect in future wireless communication systems. </div>

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.