In wireless communications, the use of multiple antennas at both the transmitter and the receiver is a key technology to enable high data rate transmission without additional bandwidth or transmit power. Multiple-input multiple-output (MIMO) schemes are widely used in many wireless standards, allowing higher throughput using spatial multiplexing techniques. MIMO soft detection poses significant challenges to the MIMO receiver design as the detection complexity increases exponentially with the number of antennas. As the next generation wireless system is pushing for multi-Gbps data rate, there is a great need for high-throughput low-complexity soft-output MIMO detector. The brute-force implementation of the optimal MIMO detection algorithm would consume enormous power and is not feasible for the current technology. We propose a reduced-complexity soft-output MIMO detector architecture based on a trellis-search method. We convert the MIMO detection problem into a shortest path problem. We introduce a path reduction and a path extension algorithm to reduce the search complexity while still maintaining sufficient soft information values for the detection. We avoid the missing counter-hypothesis problem by keeping multiple paths during the trellis search process. The proposed trellis-search algorithm is a data-parallel algorithm and is very suitable for high speed VLSI implementation. Compared with the conventional tree-search based detectors, the proposed trellis-based detector has a significant improvement in terms of detection throughput and area efficiency. The proposed MIMO detector has great potential to be applied for the next generation Gbps wireless systems by achieving very high throughput and good error performance. The soft information generated by the MIMO detector will be processed by a channel decoder, e.g. a low-density parity-check (LDPC) decoder or a Turbo decoder, to recover the original information bits. Channel decoder is another very computational-intensive block in a MIMO receiver SoC (system-on-chip). We will present high-performance LDPC decoder architectures and Turbo decoder architectures to achieve 1+ Gbps data rate. Further, a configurable decoder architecture that can be dynamically reconfigured to support both LDPC codes and Turbo codes is developed to support multiple 3G/4G wireless standards. We will present ASIC and FPGA implementation results of various MIMO detectors, LDPC decoders, and Turbo decoders. We will discuss in details the computational complexity and the throughput performance of these detectors and decoders.

FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA. Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA. The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated. All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs. Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

The contribution of this thesis is two-fold: an on-chip interconnection architecture designed specifically for multi-core processors and a tool framework that simplifies the process of designing a multi-core processor. Both contributions primarily target ASIC fabrication, though prototyping on an FPGA is also supported. SG-Multi, the on-chip interconnection architecture, distinguishes itself from other interconnection architectures by emphasizing universal adaptability; that is, a primary design goal is to ensure compatibility with industry-supplied cores originally intended for other architectures. This goal is achieved through the use of bus adapters and without introducing clock cycle latency. SG-Multi is a multi-bus architecture that uses slave-side arbitration and supports multiple simultaneous transactions between independent devices. All transactions are pipelined in two stages, an address phase and a data phase, and for improved performance slave devices must signal their status for a given clock cycle at the beginning of that cycle. SG-Multi Designer, the tool framework which builds systems that use SG-Multi, provides a higher level of abstraction compared to other competing system-building solutions; the set of components with which a designer must be concerned is much more limited, and low-level details such as hardware interface compatibility are removed from active consideration. Experimental results demonstrate that the hardware cost of using SG-Multi is reasonable compared to using a processor's native bus architecture, although the current implementation of arbitration is identifiable as an area for future improvement. It is also shown that SG-Multi is scalable; the reference systems grow linearly with respect to the number of cores when tested for ASIC fabrication and slightly sublinearly when tested for FPGA prototyping, and the maximum achievable clock frequency remains almost constant as the number of cores grows beyond four. Because the reference systems tested are an accurate reflection of the types of systems SG-Multi Designer produces, it is concluded that the abstraction model used by SG-Multi Designer does not over-simplify the design process in a way that causes excessive performance degradation or increased hardware resource consumption.

Restoring vision to the blind has been an objective of several research teams for a number of years. It is known that spots of light -- phosphenes -- can be elicited by way of electrical stimulation of surviving retinal neurons. Beyond this, however, our understanding of prosthetic vision remains rudimentary. To advance the realisation of a clinically viable prosthesis for the blind, a versatile integrated circuit neurostimulator was designed, manufactured, and verified. The neurostimulator provides electrical stimuli to surviving neurons in the visual pathway, affording blind patients some form of patterned vision; besides other benefits (independence), this limited vision would let patients distinguish between day and night (resetting their circadian rhythm). This thesis presents the development of the neurostimulator, an interdisciplinary work bridging engineering and medicine. Features of the neurostimulator include: high-voltage CMOS transistors in key circuits, to prevent voltage compliance issues due to an unknown or changing combined tissue and electrode/tissue interface impedance; simultaneous stimulation using current sources and sinks, with return electrodes configured to provide maximum charge containment at each stimulation site; stimuli delivered to a two dimensional mosaic of hexagonally packed electrodes, multiplexing current sources and sinks to allow each electrode in the whole mosaic to become a stimulation site; electrode shorting to remove excess charge accumulated during each stimulation phase. Detailed electrical testing and characterisation verified that the neurostimulator performed as specified, and comparable to, or better than, other vision prostheses neurostimulators. In addition, results from several animal experiments verified that the neurostimulator can elicit electrically evoked visual responses. The features of the neurostimulator enable research into how simultaneous electrical stimulation affects the visual neural pathways; those research results could impact other neural prosthetics research and devices.

Com o aumento da densidade de transistores devido aos avanços na tecnologia de fabricação de IC, que usam cada vez dimensões menores e a possibilidade de projetar chips cada vez mais complexos, ASIC (Application Specific Integrated Circuit) podem de fato integrar sistemas complexos em um chip, chamado de System-on-chip. O ASIC possibilita a implementação de processos (módulos) paralelos em hardware, que possibilitam atingir as velocidades de processamento digital necessárias para as aplicações que envolvem altas taxas de dados. A implementação em hardware do algoritmo Viterbi é o principal foco dessa dissertação. Este texto mostra uma breve explicação do algoritmo e mostra os resultados desta na implementação do algoritmo em software e hardware. Uma arquitetura com pipeline é proposta e uma implementação em HDL (Hardware Description Language) é mostrada. / With the increasing density of gates due to advances in the IC manufacturing technology that uses increasingly smaller feature sizes, and the possibility to design more complex systems, ASIC's (Application Specific Integrated Circuit) can in fact integrate complete systems in a single chip, namely Sysntem-on-chip. The ASIC allows the implementation of parallel processes in hardware that makes possible to reach the necessary speed for the applications that need high data rates. The hardware implementation of the Viterbi encoder algorithm is the main focus of this dissertation. The text gives a brief tutorial of the algorithm and shows the results of its implementation in software and in hardware. A pipelined architecture is proposed and implemented in HDL.

Com o aumento da densidade de transistores devido aos avanços na tecnologia de fabricação de IC, que usam cada vez dimensões menores e a possibilidade de projetar chips cada vez mais complexos, ASIC (Application Specific Integrated Circuit) podem de fato integrar sistemas complexos em um chip, chamado de System-on-chip. O ASIC possibilita a implementação de processos (módulos) paralelos em hardware, que possibilitam atingir as velocidades de processamento digital necessárias para as aplicações que envolvem altas taxas de dados. A implementação em hardware do algoritmo Viterbi é o principal foco dessa dissertação. Este texto mostra uma breve explicação do algoritmo e mostra os resultados desta na implementação do algoritmo em software e hardware. Uma arquitetura com pipeline é proposta e uma implementação em HDL (Hardware Description Language) é mostrada. / With the increasing density of gates due to advances in the IC manufacturing technology that uses increasingly smaller feature sizes, and the possibility to design more complex systems, ASIC's (Application Specific Integrated Circuit) can in fact integrate complete systems in a single chip, namely Sysntem-on-chip. The ASIC allows the implementation of parallel processes in hardware that makes possible to reach the necessary speed for the applications that need high data rates. The hardware implementation of the Viterbi encoder algorithm is the main focus of this dissertation. The text gives a brief tutorial of the algorithm and shows the results of its implementation in software and in hardware. A pipelined architecture is proposed and implemented in HDL.

The purpose of the thesis was to investigate and evaluate existing algorithms for division of complex numbers. The investigation should include implementation of a few suitable algorithms in VHDL. The main application for the divider is compensation for fading in a baseband processor. Since not much public research is done within the area of complex division in hardware, a divider based on real valued division was designed. The design only implements inversion of complex numbers instead of complete division because it is simpler and the application does not need full division, thus the required chip size is reduced. An examination of the different kinds of algorithms that exists for real valued division was done and two of the methods were found suitable for implementation, digit recurrence and functional iteration. From each of the two classes of algorithms one algorithm was chosen and implemented in VHDL. Two different versions of the inverter were designed for each method, one with full throughput and one with half throughput. The implementations show very similar results in terms of speed, size and performance. For most cases however, the digit recurrence implementation has a slight advantage.

Com o aumento da densidade de transistores devido aos avanços na tecnologia de fabricação de IC, que usam cada vez dimensões menores e a possibilidade de projetar chips cada vez mais complexos, ASIC (Application Specific Integrated Circuit) podem de fato integrar sistemas complexos em um chip, chamado de System-on-chip. O ASIC possibilita a implementação de processos (módulos) paralelos em hardware, que possibilitam atingir as velocidades de processamento digital necessárias para as aplicações que envolvem altas taxas de dados. A implementação em hardware do algoritmo Viterbi é o principal foco dessa dissertação. Este texto mostra uma breve explicação do algoritmo e mostra os resultados desta na implementação do algoritmo em software e hardware. Uma arquitetura com pipeline é proposta e uma implementação em HDL (Hardware Description Language) é mostrada. / With the increasing density of gates due to advances in the IC manufacturing technology that uses increasingly smaller feature sizes, and the possibility to design more complex systems, ASIC's (Application Specific Integrated Circuit) can in fact integrate complete systems in a single chip, namely Sysntem-on-chip. The ASIC allows the implementation of parallel processes in hardware that makes possible to reach the necessary speed for the applications that need high data rates. The hardware implementation of the Viterbi encoder algorithm is the main focus of this dissertation. The text gives a brief tutorial of the algorithm and shows the results of its implementation in software and in hardware. A pipelined architecture is proposed and implemented in HDL.

Les réseaux de capteurs sans fil (WSN) ont attiré un grand intérêt dans la dernière décennie, et ont apporté des solutions dans un nombre croissant d’applications. Toutefois, certaines d’entre elles restent irréalisables en raison de forts points de blocage non résolus, comme un manque de synchronisation entre les prises de mesures, ainsi que des débits de données trop faibles. Ce travail apporte une solution à ces deux points majeurs via la conception d’un noeud communicant sans fil spécifique. Celle ci, basée sur la conception croisée, utilise les propriétés temporelles des modulations UltraLarge Bande (UWB) pour permettre une synchronisation très précise ainsi qu’un débit de données élevé. Notre démonstrateur ASIC basé sur ces travaux permet une précision de synchronisation de 2 ns pour une modulation IR-UWB sur une bande passante de 1,5 GHz. Cette thèse décrit le protocole de synchronisation WiDeCS et la conception de deux preuves de concept fonctionnelles sur FPGA et ASIC / Wireless Sensor Networks have attracted mutch interest in the last decade, opening a new range of applications such as large area monitoring. However, a range of possible applications is still not satisfied due to strong blocking points remaining unsolved such as the lack of synchronization between measurements and low attain- able data rates. This doctoral work aims at solving these two issues issue through the design of a Wireless Sensor node implementation. The proposed solution is based on cross-layer design and uses time-domain properties of UltraWide Band (UWB) to provide nanosecond-scale synchronization between nodes and high data- rate transmission. An ASIC implementation has been designed, and demonstrates a 2 ns synchronization error with IR-UWB modulation over a 1.5 GHz bandwidth. In this thesis, a cross-layer scheme named WiDeCS is proposed, and two proof of concept implementations are detailed.

Charge detection is essential for a large number of commercial and scientific applications. A charge amplifier is one of the most fundamental building blocks for a detector system. This thesis describes the design, circuit implementation, and post-silicon testing of two different charge amplifier designs, analog and digital, that address some commonly seen fundamental challenges in the charge detection application. In particular, the proposed designs can be integrated with an image charge detector (ICD) to study the characteristics of dust on Mars. The proposed charge amplifier design utilizes a small 10 fF feedback capacitor to achieve a high gain. The fully integrated custom differential charge amplifier design improves the accuracy and robustness of its charge gain, and provides a compact method to extract detector capacitance for gain calibration. Conventional charge amplifiers' charge-to-voltage gain is a function of the detector parasitic capacitance. Therefore, a high precision photo-current calibration method is proposed here to enable an accurate gain calibration. In addition, a novel "digital amplifier" with close to rail-to-rail output swing is proposed to realize an infinite equivalent open-loop gain. Consisting of an ADC and charge pump as the amplifier core, this proposed design maintains a consistent closed-loop gain independent of the input parasitic capacitance. The ADC is realized as a single comparator, i.e. a 1-bit ADC, which, together with an SR latch and a differential charge pump, replaces the conventional analog amplifier core.