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In Part I, the design of an ASIC control chip for a forward active clamp converter is presented. Integration of the control and drive circuit into one IC chip results in higher power density, higher reliability for the converter module. The designed ASIC control chip uses a 2.0 um N well Analog CMOS process, and is fabricated at MOSIS. The design procedures of the ASIC chip are explained, and experimental results are presented. Part II of the thesis focuses on the numerical investigation of several integratable lateral power devices. Lateral power devices are used in power IC designs because of their compatibility with analog & digital IC process. To obtain devices with high current density, large safe operating area, fast response and low cost is highly desirable for power ICs. In Part II of this thesis, several lateral power devices are discussed and simulated, including lateral IGBT, lateral MCT and double gate lateral MCTs. It is shown that lateral IGBT and lateral MCTs are good candidates for power IC applications. / Master of Science

In the last few decades, secure algorithms have played an irreplaceable role in the protection of private information, such as applications of AES on modems, as well as online bank transactions. The increasing application of secure algorithms on hardware has made implementations on ASIC benchmarks extremely important. Although all kinds of secure algorithms have been implemented into various devices, the effects from different constraints on ASIC implementation performance have never been explored before. In order to analyze the effects from different constraints for secure algorithms, SHA-3 finalists, which includes Blake, Groestl, Keccak, JH, and Skein, have been chosen as the ones to be implemented for experiments in this thesis. This thesis has first explored the effects of different synthesis constraints on ASIC performance, such as the analysis of performance when it is constrained for frequency, or maximum area, etc. After that, the effects of choosing various standard libraries were tested, for instance, the performance of UMC 130nm and IBM 130nm standard libraries have been compared. Additionally, the effects of different technologies have been analyzed, such as 65nm, 90nm, 130nm and 180nm of UMC libraries. Finally, in order to further understand the effects, experiments for post-layout analysis has been explored. While some algorithms remain unaffected by floor plan shapes, others have shown preference for a specific shape, such as JH, which shows a 12% increase in throughput/area with a 1:2 rectangle compared to a square. Throughout this thesis, the effects of different ASIC implementation factors have been comprehensively explored, as well as the details of the methodology, metrics, and the framework of the experiments. Finally, detailed experiment results and analysis will be discussed in the following chapters. / Master of Science

Depuis plusieurs années, les composants dédiés à la sécurité comme les cartes à puce sont soumises à des attaques dites par canaux cachés. Ces attaques permettent d'exhiber les secrets en analysant des caractéristiques physiques comme la consommation du composant ou encore son temps d'exécution. Dans le cadre de cette thèse, deux contremesures ont été réalisées et appliquées à l'AES (algorithme de chiffrement symétrique). De plus, afin d'aider les développements futurs des contremesures et la validation de celles-ci, un simulateur a été développé. Il permet de réaliser des attaques grâce à un modèle de consommation défini dans les phases amont de développement. Enfin, j'ai pu participer aux groupes de travail qui ont proposé Shabal à la compétition SHA-3, qui vise à définir un nouveau standard pour les fonctions de hachage. Des implantations matérielles ont été réalisées par la suite. / For several years, the security components such as smart cards are subject to side channel attacks. These attacks allow to exhibit secrets by analyzing the physical characteristics such as power consumption or execution time. As part of this thesis, two countermeasures were carried out and applied to the AES (symmetric cipher). In addition, to help future development of countermeasures and their validation, a simulator was developed. It realizes attacks using a power consumption model defined in the early phases of development. Finally, I participated in working groups that have proposed Shabal to SHA-3 competition, which aims to define a new standard for hash functions. Hardware implementations have been made thereafter.

Primitivas criptografias assimétricas são essenciais para conseguir comunicação segura numa rede ou meio público. Essas primitivas podem ser instaladas como bibliotecas de software ou como coprocessadores de hardware. Coprocessadores de hardware são muito utilizados em cenários como Systems on Chip (SoC), dispositivos embarcados ou servidores de aplicações específicas. Coprocessadores existentes baseados em RSA ou curvas ellipticas (ECC) fazem um processamento intenso por causa da aritmética modular de grande precisão, portanto não estão disponíveis em plataformas com quantidade de energia mais restrita. Para prover primitivas assimétricas para esses dispositivos, será avaliado um esquema de cifração assimétrica que utiliza artimética de pequena precisão, chamado McEliece. McEliece foi proposto com códigos de Goppa binários durante o mesmo ano que o RSA, porém com chaves públicas 50 vezes maiores. Por causa de chaves tão grandes ele não ganhou muita atenção como RSA e ECC. Com a adoção de códigos Quase-Diádicos de Goppa binários é possível obter níveis de segurança práticos com chaves relativamente pequenas. Para avaliar uma implementação em hardware para esse esquema, foi proposto uma arquitetura escalável que pode ser configurada de acordo com os requisitos do projeto. Essa arquitetura pode ser utilizada em todos os níveis de segurança, de 80 até 256 bits de segurança, da menor unidade até as maiores. Nossa arquitetura foi implementada na família de FPGAs Spartan 3 para códigos de Goppa binários, onde foi possível decifrar em 5854 ciclos com 4671 Slices, enquanto que na literatura os melhores resultados obtidos são de 10940 ciclos para 7331 Slices. / Asymmetric cryptographic primitives are essential to enable secure communications on public networks or public mediums. These cryptographic primitives can be deployed as software libraries or hardware coprocessors. Hardware coprocessors are mostly employed in Systems on Chip (SoC) scenarios, embedded devices, or application-specific servers. Available solutions based on RSA or Elliptic Curve Cryptography (ECC) are highly processing intensive because of the underlying extended precision modular arithmetic, and hence they are not available on the most energy constrained platforms. To provide asymmetric primitives in those restricted devices, we evaluate another asymmetric encryption scheme implementable with lightweight arithmetic, called McEliece. McEliece was proposed with binary Goppa codes during same year of RSA with public keys 50 times larger. Because of such large keys it has not gained as much attention as RSA or ECC. With the adoption of binary Quasi- Dyadic Goppa (QD-Goppa) codes it is possible to attain practical security levels with reasonably small keys. To evaluate a hardware implementation of this scheme, we investigate a scalable architecture that can be reconfigured according to project requirements. This architecture is suitable for all usual security levels, from 80 to 256-bit security, from the smallest unit to bigger ones. With our architecture implemented on a Spartan 3 FPGA for binary Goppa codes it is possible to decrypt in 5854 cycles with 4671 Slices, whilst in literature best results were in 10940 cycles with 7331 Slices.

Primitivas criptografias assimétricas são essenciais para conseguir comunicação segura numa rede ou meio público. Essas primitivas podem ser instaladas como bibliotecas de software ou como coprocessadores de hardware. Coprocessadores de hardware são muito utilizados em cenários como Systems on Chip (SoC), dispositivos embarcados ou servidores de aplicações específicas. Coprocessadores existentes baseados em RSA ou curvas ellipticas (ECC) fazem um processamento intenso por causa da aritmética modular de grande precisão, portanto não estão disponíveis em plataformas com quantidade de energia mais restrita. Para prover primitivas assimétricas para esses dispositivos, será avaliado um esquema de cifração assimétrica que utiliza artimética de pequena precisão, chamado McEliece. McEliece foi proposto com códigos de Goppa binários durante o mesmo ano que o RSA, porém com chaves públicas 50 vezes maiores. Por causa de chaves tão grandes ele não ganhou muita atenção como RSA e ECC. Com a adoção de códigos Quase-Diádicos de Goppa binários é possível obter níveis de segurança práticos com chaves relativamente pequenas. Para avaliar uma implementação em hardware para esse esquema, foi proposto uma arquitetura escalável que pode ser configurada de acordo com os requisitos do projeto. Essa arquitetura pode ser utilizada em todos os níveis de segurança, de 80 até 256 bits de segurança, da menor unidade até as maiores. Nossa arquitetura foi implementada na família de FPGAs Spartan 3 para códigos de Goppa binários, onde foi possível decifrar em 5854 ciclos com 4671 Slices, enquanto que na literatura os melhores resultados obtidos são de 10940 ciclos para 7331 Slices. / Asymmetric cryptographic primitives are essential to enable secure communications on public networks or public mediums. These cryptographic primitives can be deployed as software libraries or hardware coprocessors. Hardware coprocessors are mostly employed in Systems on Chip (SoC) scenarios, embedded devices, or application-specific servers. Available solutions based on RSA or Elliptic Curve Cryptography (ECC) are highly processing intensive because of the underlying extended precision modular arithmetic, and hence they are not available on the most energy constrained platforms. To provide asymmetric primitives in those restricted devices, we evaluate another asymmetric encryption scheme implementable with lightweight arithmetic, called McEliece. McEliece was proposed with binary Goppa codes during same year of RSA with public keys 50 times larger. Because of such large keys it has not gained as much attention as RSA or ECC. With the adoption of binary Quasi- Dyadic Goppa (QD-Goppa) codes it is possible to attain practical security levels with reasonably small keys. To evaluate a hardware implementation of this scheme, we investigate a scalable architecture that can be reconfigured according to project requirements. This architecture is suitable for all usual security levels, from 80 to 256-bit security, from the smallest unit to bigger ones. With our architecture implemented on a Spartan 3 FPGA for binary Goppa codes it is possible to decrypt in 5854 cycles with 4671 Slices, whilst in literature best results were in 10940 cycles with 7331 Slices.

La migraine est un désordre neurovasculaire caractérisé par des crises récurrentes de céphalée accompagnées de troubles neurologiques variables dont l'allodynie cutanée.Chez un petit nombre de patients, la migraine passe du stade épisiodique au stade chronique, ou transformation migraineuse. Des études cliniques indiquent que la prévalence de troubles psychiatriques( anxiété/dépression) est plus élevé chez les migraineux chronique que chez le migraineux épisodique. Cependant des telles études ne permettent pas de déterminer le lien de causalité. Le but de ce travail est d'étudier le rôle de la répétition des crises de migraine sur l'apparition d'un état anxio-dépressif et ses mécanismes. Cette étude a été réalisée dans un modèle de migraine chez le rat : injections répétées de soupe inflammatoire (SI) au niveau des méninges.[...]Ces résultats suggèrent que l'apparition de troubles anxio-dépressifs chez le migraineux chronique est une conséquence directe de la répétition des crises. Cette anxiété résulte, entres autres, d'une sensiblisation du MeA impliquant les canaux ASICS1a. Ainsi élucider les mécanismes impliqués dans l'apparition de troubles anxio-dépressifs doit aider à comprendre la transformation migraineuse et améliorer son traitement. / Migraine is a common episode neurovascular disorder that manifest as reccurent attacks of severe headache together with variable neurological symptômes such as cutaneous allodyna. In subgroup of patients, attack frequency increases over time leading to chronic migraine. Clinical studies indicate that patients with episodic migraine are more likely to have anxiety symptoms than patients with episodic migraine..However, in cross-sectional studies, it is not possible to disentangle causal sequence. Our aim is to assess the role oh headache repetition on anxiety/depression symptoms. We use a rat model of migraine : stimulation of meningeal nociceptors by injecting an inflammatory soup (SI)[...]Such anxiety is due, at least in part, to MeA, sensitization involving ASIC1a channels. Dissecting out the mechanisms of the appearance of anxiety/depression symptoms following repeated migraine attacks in thus helping to understand migraine transformation and in turn to improve therapy.