Computer has evolved rapidly during the past several decades in terms of its implementation technology; it's architecture, however, has not changed dramatically since the von Neumann computer(control flow) model emerged in the 1940s. One main reason is that the performance for this kind of computers was able to satisfy the requirement of most users. Another reason maybe that the engineers who designed them are more familiar with this model. However, recent solutions to the problem of parallelizing sequential nature instructions on a von Neumann machine complicate both the compiler and the controller design. Therefore, another computer model, namely the data flow model, has regained attention since this model of computation exposes parallelism inherent in the program naturally. In terms of implementation methodology, we currently use synchronous sequential logic, which is clock controlled for synchronization within circuits. This design philosophy becomes hard to follow due to the occurrence of clock skew as the clock frequency goes higher and higher. One way to eliminate these clock related problems is to use the self-timed(asynchronous) implementation methodology. It features advantages such as free of clock-skew, low power consumption, composibility and so forth. Since data flow(data driven) computation model provides the execution of instructions asynchronously, it is natural to implement a data flow processor using self-timed circuits. In this thesis, micro pipelines, one of the self-timed implementation methodology, is used to implement a preliminary version of general purpose static data flow processor. Some interesting observations will be addressed in this thesis. An example program of general difference recursive equation is given to test the correctness and performance of this processor. We hope to gain more insight on how to design and implement self-timed systems in the future. / Graduation date: 1994

With the increased demand for complex digital signal processing systems, real-time signal processing requires higher throughput systems. In the past, the throughput has been increased by increasing the clock rates, but synchronization can become increasingly more difficult. Recently there has been renewed interest in designing asynchronous digital systems. In an asynchronous system, there is no global clock, and all modules communicate through handshaking. In this thesis we demonstrate an implementation of an FIR filter using asynchronous digital circuit techniques. These asynchronous design techniques are used to test whether a practical signal processing filter can be implemented with asynchronous logic. A third-order four-bit filter is developed and simulated with SPICE, comparing favorably with other available technologies in speed and power consumption. Although in practice 8-16 bits are needed, this work is sufficient to demonstrate the feasibility of asynchronous circuits for filtering applications. A chip is laid out in 2 micron CMOS, and testing shows that it has a speed-power product comparable with asynchronous designs fabricated by others. / Graduation date: 1994

Ph.D. / Electrical Engineering / The expected unreliability of nano-scale electronic components has renewed interest in the decades-old field of fault-tolerant logic design. Fault-tolerant design makes it possible to build reliable systems from unreliable components. This has spurred recent research into the application of classical FT techniques to nanoelectronics. Meanwhile, the growing gap between logic gate and wire delays, and the growing power consumption of clock generation and distribution circuits, in nanometer-scale silicon integrated circuits has renewed research in asynchronous, or clockless, logic design. This dissertation examines the application of triple modular redundancy (TMR), one of several FT circuit design techniques, to improve the reliability of a variety of clockless circuits and systems. A new fault model, appropriate for clockless circuits is derived and applied to measure the reliability of nonredundant and triplex micropipelines. A new circuit element that combines the functionality of a Muller C-element and a majority gate is introduced to solve special problems at the simplex-triplex interface. The effectiveness of asynchronous FT circuit design strategies based on the results of Monte Carlo simulation experiments with representative circuits modeled in Verilog hardware description language (HDL) is presented.

This paper designs and implements a DSP based Multi-function Monitoring Control System, operate for induction motor, intelligent battery charger and residual capacity estimator and Uninterrupt Power System to develop effectively and complete well. This paper that Multi-function Monitoring Control System set up RS-232 standard, to use Asynchronous Receiver Transmitter Communication, to use DSP software refinement, to solve using ¡§8250¡¨ that Communication IC complete PC and DSP Communication generally. And DSP software monitor and control that induction motor, intelligent battery charger and residual capacity estimator and Uninterrupt Power System well. Monitoring control system utilize DSP operate very fast¡Aso DSP software function to supply hardware work¡Ato reduce prime cost.

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State-of-the-art multi-processor systems-on-chip use on-chip networks as their communication fabric. Although most on-chip networks are implemented synchronously, asynchronous on-chip networks have several advantages over their synchronous counterparts. Timing division multiplexing (TDM) flow control methods have been utilized in asynchronous on-chip networks extensively. The synchronization required by TDM leads to significant speed penalties. Compared with using TDM methods, spatial parallelism methods, such as the spatial division multiplexing (SDM) flow control method, achieve better network throughput with less area overhead.This thesis proposes several techniques to increase spatial parallelism in the routers of asynchronous on-chip networks.Channel slicing is a new pipeline structure that alleviates the speed penalty by removing the synchronization among bit-level data pipelines. It is also found out that the lookahead pipeline using early evaluated acknowledgement can be used in routers to further improve speed.SDM is a new flow control method proposed for asynchronous on-chip networks. It improves network throughput without introducing synchronization among buffers of different frames, which is required by TDM methods. It is also found that the area overhead of SDM is smaller than the virtual channel (VC) flow control method -- the most used TDM method. The major design problem of SDM is the area consuming crossbars. A novel 2-stage Clos switch structure is proposed to replace the crossbar in SDM routers, which significantly reduces the area overhead. This Clos switch is dynamically reconfigured by a new asynchronous Clos scheduler.Several asynchronous SDM routers are implemented using these new techniques. An asynchronous VC router is also reproduced for comparison. Performance analyses show that the SDM routers outperform the VC router in throughput, area overhead and energy efficiency.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / This paper will describe a test technique developed to measure the delays caused by the use of asynchronous multiplexers/demultiplexers. These devices are used for both signal transmission (microwave and fiber optic) and signal recording (especially helical scan digital recorders). The test technique involves the generation and decoding of asynchronous telemetry signals. The bit rates of the telemetry signals are variable. Relative time is embedded in the telemetry signal as a 32-bit data word. The paper will also present measured delays for two multiplexers/demultiplexers for different combinations of bit rates.

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