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The effective performance of computer systems is to a large measure determined by the synergy between the processor architecture, the instruction set and the compiler. In the past, the sequencing of information within processor architectures has normally been synchronous: controlled centrally by a clock. However, this global signal could possibly limit the future gains in performance that can potentially be achieved through improvements in implementation technology. This thesis investigates the effects of relaxing this strict synchrony by distributing control within processor architectures through the use of a novel asynchronous design model known as a micronet. The impact of asynchronous control on the performance of a RISC-style processor is explored at different levels. Firstly, improvements in the performance of individual instructions by exploiting actual run-time behaviours are demonstrated. Secondly, it is shown that micronets are able to exploit further (both spatial and temporal) instructionlevel parallelism (ILP) efficiently through the distribution of control to datapath resources. Finally, exposing fine-grain concurrency within a datapath can only be of benefit to a computer system if it can easily be exploited by the compiler. Although compilers for micronet-based asynchronous processors may be considered to be more complex than their synchronous counterparts, it is shown that the variable execution time of an instruction does not adversely affect the compiler's ability to schedule code efficiently. In conclusion, the modelling of a processor's datapath as a micronet permits the exploitation of both finegrain ILP and actual run-time delays, thus leading to the efficient utilisation of functional units and in turn resulting in an improvement in overall system performance.

The emerging high-speed Asynchronous Transfer Mode (ATM) networks are expected to integrate through statistical multiplexing large numbers of traffic sources having a broad range of statistical characteristics and different Quality of Service (QOS) requirements. To achieve high utilisation of network resources while maintaining the QOS, efficient traffic management strategies have to be developed. This thesis considers the problem of traffic control for ATM networks. The thesis studies the application of neural networks to various ATM traffic control issues such as feedback congestion control, traffic characterization, bandwidth estimation, and Call Admission Control (CAC). A novel adaptive congestion control approach based on a neural network that uses reinforcement learning is developed. It is shown that the neural controller is very effective in providing general QOS control. A Finite Impulse Response (FIR) neural network is proposed to adaptively predict the traffic arrival process by learning the relationship between the past and future traffic variations. On the basis of this prediction, a feedback flow control scheme at input access nodes of the network is presented. Simulation results demonstrate significant performance improvement over conventional control mechanisms. In addition, an accurate yet computationally efficient approach to effective bandwidth estimation for multiplexed connections is investigated. In this method, a feed forward neural network is employed to model the nonlinear relationship between the effective bandwidth and the traffic situations and a QOS measure. Applications of this approach to admission control, bandwidth allocation and dynamic routing are also discussed. A detailed investigation has indicated that CAC schemes based on effective bandwidth approximation can be very conservative and prevent optimal use of network resources. A modified effective bandwidth CAC approach is therefore proposed to overcome the drawback of conventional methods. Considering statistical multiplexing between traffic sources, we directly calculate the effective bandwidth of the aggregate traffic which is modelled by a two-state Markov modulated Poisson process via matching four important statistics. We use the theory of large deviations to provide a unified description of effective bandwidths for various traffic sources and the associated ATM multiplexer queueing performance approximations, illustrating their strengths and limitations. In addition, a more accurate estimation method for ATM QOS parameters based on the Bahadur-Rao theorem is proposed, which is a refinement of the original effective bandwidth approximation and can lead to higher link utilisation.

Problema de Investigación Hay mucha dificultad en implementar la interfaz ICallbackEventHandler cuando se desea agregar varias llamadas asíncronas en una misma página web. Existen una serie de pasos que se deben realizar cada vez que se quiera ejecutar un evento que tenga las características asíncronas utilizando ICallbackEventHandler, esto demanda un exceso de tiempo y esfuerzo que podría ser reducido. A continuación se describen los pasos: a) Implementar la interface b) Implementar los métodos de la interface c) Colocar el script del servidor d) Colocar el script del lado del cliente e) Modificar los métodos de la interface según el funcionamiento que se desea obtener. f) Realizar llamada asíncrona Este es justamente el problema que se ha encontrado y se atacará, para reducir los pasos y dar facilidad para implementar más eventos en una misma interfaz de una manera más fácil y rápida. Objetivo General Bajar la dificultad de uso de ICallbackEventHandler al desarrollar páginas Web. Se reduce la implementación a un mínimo de 4 pasos que además son más óptimos. Objetivos Específicos a) Usar varios métodos personalizables en la aplicación, ocultando los métodos en el lado del servidor: RaiseCallbackEvent y GetCallbackResult. b) Permitir que los métodos personalizables tengan varios parámetros de tipos numéricos y tipo String. c) Facilitar la tarea de implementar más de una llamada asíncrona. Se cuenta con métodos indefinidos en el servidor d) Permitir controlar las Excepciones e) Utilizar la función estándar “ICallBackFunction” para la comunicación con el servidor

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Chan Wing-kin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 69-72). / Abstracts in English and Chinese. / Abstract of this thesis entitled: --- p.ii / 摘要 --- p.iv / Acknowledgements --- p.v / Table of Contents --- p.vi / List of Figures --- p.viii / List of Tables --- p.x / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview of Communication Systems --- p.1 / Chapter 1.2 --- Soft-output Viterbi Decoder and Turbo Code --- p.2 / Chapter 1.3 --- Iterative Decoding --- p.3 / Chapter 1.4 --- Motivation --- p.3 / Chapter 1.5 --- Organization of the Thesis --- p.4 / Chapter Chapter 2 --- Self-timed Circuit Design Methodology --- p.5 / Chapter 2.1 --- Properties of Self-Timed Design --- p.5 / Chapter 2.2 --- Bundled-data Protocol --- p.7 / Chapter 2.3 --- Two-phase verses Four-phase Handshaking --- p.8 / Chapter 2.4 --- Completion-Detection and Delay Match --- p.9 / Chapter 2.5 --- Muller Pipeline --- p.11 / Chapter 2.6 --- Design of the Adder --- p.12 / Chapter 2.6.1 --- Basic Structure --- p.12 / Chapter 2.6.2 --- Carry Chain and Completion Detection --- p.12 / Chapter Chapter 3 --- SOVA Theory --- p.15 / Chapter 3.1 --- Convolutional Encoder --- p.15 / Chapter 3.2 --- Hard verse Soft Decision Decoding --- p.17 / Chapter 3.3 --- Soft Output Viterbi Algorithm --- p.17 / Chapter 3.3.1 --- Viterbi Algorithm --- p.17 / Chapter 3.3.2 --- Soft Output Algorithm --- p.20 / Chapter Chapter 4 --- Proposed SOVA Decoder Design --- p.24 / Chapter 4.1 --- Overview --- p.24 / Chapter 4.2 --- SOVA Decoder Architecture --- p.24 / Chapter 4.3 --- Branch Metric Unit --- p.26 / Chapter 4.3.1 --- Branch Metric Generation --- p.26 / Chapter 4.3.2 --- Implementation --- p.27 / Chapter 4.4 --- Add-Compare-Select Unit --- p.28 / Chapter 4.4.1 --- Basics --- p.28 / Chapter 4.4.2 --- Self-timed design --- p.28 / Chapter 4.4.3 --- Metric Normalization --- p.30 / Chapter 4.4.4 --- ACS Unit Implementation --- p.31 / Chapter 4.5 --- Traceback Unit --- p.33 / Chapter 4.5.1 --- Viterbi Algorithm Traceback --- p.33 / Chapter 4.5.2 --- Two Step SOVA --- p.34 / Chapter 4.5.3 --- Past Designs --- p.36 / Chapter 4.5.4 --- New Traceback Architecture --- p.38 / Chapter 4.5.5 --- Traceback operation --- p.40 / Chapter 4.5.6 --- Traceback Implementation --- p.42 / Chapter 4.5.7 --- Control Signals --- p.48 / Chapter Chapter 5 --- Experimental Result and Discussion --- p.54 / Chapter 5.1 --- Chip Fabrication --- p.54 / Chapter 5.2 --- Measurements --- p.61 / Chapter Chapter 6 --- Conclusion --- p.67 / References --- p.69 / Appendix --- p.73 / Pin Assignment of the SOVA test chip --- p.73

The counterflow pipeline concept was originated by Sproull et. al.[1] to demonstrate the concept of asynchronous circuits. The basic premise is that a simple architecture with only local communication and control and a simple regular structure will result in increased performance. This thesis attempts to analyze the performance of the basic counterflow pipeline architecture, find the bottlenecks associated with this implementation, and attempt to illustrate the improvements that we have made in overcoming these bottlenecks. From this research, three distinct microarchitectures have been developed, ranging from a synchronous version of the counterflow design suggested by Sproull to an all new structure which supports aggressive speculation, no instruction stalling and ultimately intrinsic multi-threading. To support high-level simulation of various architectures a Java based simulation environment has been developed which was used to explore the various design trade-offs and evaluate the resulting performance of each of the architectures. / Graduation date: 1998

Asynchronous circuits have recently been a breakthrough in many high performance computers. The concept of asynchronous circuits which started a long time ago has slowly grasped the attention of many designers. The Muller-C-element is an important control block in many asynchronous designs and therefore it is important to understand some of the possible failures that might occur in this circuit. The timing and behavior of this element will have an important effect on the overall performance of the system. The purpose of this research is to study some of the common failures that exist in synchronous logic and find out if these failures can also happen in the C-element. Condition for a failure must be present in order for it to occur. Understanding the conditions required for a circuit failure to occur, we will show realistic examples in the applications of C-element in which such similar conditions will also happen. In this thesis, we are interested in analyzing the circuit failures in C-element due to different logic threshold voltages of different devices, problem of charge-sharing and metastabilty characteristic of circuit. Simulations results will show such failures does occur in the C-element when the conditions were met. / Graduation date: 1997

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered or mobile applications which need medium resolution (8-12 bits), medium speed (10 - 100 MS/s) and require low-power consumption and small form factor. This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC’s analog components – comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 µm. Design’s noise and power are presented as a breakdown among components. / text

Microprocessor systems have been advancing at a phenomenal rate, with each new generation introducing improved fabrication processes and architectural innovations. Unfortunately, traditional fabrication techniques cannot sustain this exponential growth indefinitely. Thus, additional research into conventional design methodologies, such as those involving asynchronous design techniques, is essential to maintain the current trend. The primary objective of this research was to explore the viability of asynchronous design techniques as an alternative to current synchronous design methods. In order to simulate the design complexities involved in a real-world system, the MIPS-II R2000 pipelined microprocessor was selected as the basis for comparison. All of the experimental processors were designed in VHDL on an FPGA using the Altera Quartus II design package. The processors were tested using timing simulations with various benchmarks to determine the advantages and disadvantages of each design technique. Four distinct asynchronous processors with varying handshaking and synchronization methods were designed and compared to the baseline synchronous processor. Although, in theory, each of the asynchronous design variations had its merits, it was clear that not all of them were well suited for practical use in a large-scale microprocessor environment. Three of the asynchronous processors suffered from an excessive amount of synchronization overhead that drastically reduced their overall system performance to the point where they performed considerably worse than the baseline synchronous processor. However, one asynchronous processor performed considerably better: with only a 1.5 percent increase in logic complexity, it outperformed the baseline synchronous processor by over 10 percent on a sorting test benchmark and had a maximum theoretical speedup of over 36 percent. Therefore, it is evident that asynchronous designs have the potential to improve the performance of traditional synchronous systems. However, designing efficient and hazard-free asynchronous logic on an FPGA proved to be challenging and time-consuming. With additional research and further design tool improvements to facilitate the creation of optimized glitch-free logic, asynchronous design methodologies may become a viable alternative to traditional synchronous designs and contribute to the current trend of microprocessor advancement. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-12-19 01:30:22.248