Rapid progress over the last decade on large area thin film transistor (TFT) arrays led to the emergence of high-performance, low-power, low-cost active matrix flat panel imagers. Despite the shortcomings associated with the instability and low mobility of TFTs, the amorphous silicon TFT technology still remains the primary solution for the backplane of flat panel imagers. The use of a-Si:H TFTs as the building block of the large area integrated circuit becomes challenging particularly when the role of the TFT is extended from traditional switching applications to on-pixel signal amplifier for large area digital imaging. This is the idea behind active pixel sensor (APS) architectures in which under each pixel an amplifier circuit consisting of one or two switching TFTs integrated with one amplifying TFT is fabricated. To take advantage of the full potential of these amplifiers, it is crucial to develop APS architectures to compensate for the limitations of the TFTs. In this thesis several APS architectures are designed, simulated, fabricated, and tested addressing these challenges using the mask sets presented in Appendix A. The proposed APS architectures can compensate for inherent stabilities of the comprising TFTs. Therefore, the sensitivity of their output data to the transistor variations is significantly suppressed. This is achieved by using a well defined external current source instead of the traditional voltage source to reset the APS architectures during the reset cycle of their periodic operation. The performance of these circuits is analyzed in terms of their stability, settling time, noise, and temperature-dependence. For appropriate readout of the current mode APS architectures, high gain transresistance amplifiers with correlated double sampling capability is designed, simulated and fabricated in CMOS technology. Measurement and measurement based calculation results reveal that the proposed APS architectures can meet even the stringent requirements of low noise, real-time digital fluoroscopy.

Rapid progress over the last decade on large area thin film transistor (TFT) arrays led to the emergence of high-performance, low-power, low-cost active matrix flat panel imagers. Despite the shortcomings associated with the instability and low mobility of TFTs, the amorphous silicon TFT technology still remains the primary solution for the backplane of flat panel imagers. The use of a-Si:H TFTs as the building block of the large area integrated circuit becomes challenging particularly when the role of the TFT is extended from traditional switching applications to on-pixel signal amplifier for large area digital imaging. This is the idea behind active pixel sensor (APS) architectures in which under each pixel an amplifier circuit consisting of one or two switching TFTs integrated with one amplifying TFT is fabricated. To take advantage of the full potential of these amplifiers, it is crucial to develop APS architectures to compensate for the limitations of the TFTs. In this thesis several APS architectures are designed, simulated, fabricated, and tested addressing these challenges using the mask sets presented in Appendix A. The proposed APS architectures can compensate for inherent stabilities of the comprising TFTs. Therefore, the sensitivity of their output data to the transistor variations is significantly suppressed. This is achieved by using a well defined external current source instead of the traditional voltage source to reset the APS architectures during the reset cycle of their periodic operation. The performance of these circuits is analyzed in terms of their stability, settling time, noise, and temperature-dependence. For appropriate readout of the current mode APS architectures, high gain transresistance amplifiers with correlated double sampling capability is designed, simulated and fabricated in CMOS technology. Measurement and measurement based calculation results reveal that the proposed APS architectures can meet even the stringent requirements of low noise, real-time digital fluoroscopy.

Image sensors play a vital role in many image sensing and capture applications. Among the various types of image sensors, complementary metal oxide semiconductor (CMOS) based active pixel sensors (APS), which are characterized by reduced pixel size, give fast readouts and reduced noise. APS are used in many applications such as mobile cameras, digital cameras, Webcams, and many consumer, commercial and scientific applications. With these developments and applications, CMOS APS designs are challenging the old and mature technology of charged couple device (CCD) sensors. With the continuous improvements of APS architecture, pixel designs, along with the development of nanometer CMOS fabrications technologies, APS are optimized for optical sensing. In addition, APS offers very low-power and low-voltage operations and is suitable for monolithic integration, thus allowing manufacturers to integrate more functionality on the array and building low-cost camera-on-a-chip. In this thesis, I explore the current state-of-the-art of CMOS APS by examining various types of APS. I show design and simulation results of one of the most commonly used APS in consumer applications, i.e. photodiode based APS. We also present an approach for technology scaling of the devices in photodiode APS to present CMOS technologies. Finally, I present the most modern CMOS APS technologies by reviewing different design models. The design of the photodiode APS is implemented using commercial CAD tools.

Monolithic Active Pixel Sensors (MAPS) are good candidates to be used in High Energy Physics (HEP) experiments for charged particle detection. In the HEP applications, MAPS chips are placed very close to the interaction point and are directly exposed to harsh environmental radiation. This thesis focuses on the study and improvement of the MAPS radiation hardness. The main radiation effects and the research progress of MAPS are studied firstly. During the study, the SRAM IP cores built in MAPS are found limiting the radiation hardness of the whole MAPS chips. Consequently, in order to improve the radiation hardness of MAPS, three radiation hard memories are designed and evaluated for the HEP experiments. In order to replace the SRAM IP cores, a radiation hard SRAM is developed on a very limited area. For smaller feature size processes, in which the single event upset (SEU) effects get significant, a radiation hard SRAM with enhanced SEU tolerance is implemented by an error detection and correction algorithm and a bit-interleaving storage. In order to obtain higher radiation tolerance and higher circuitry density, a dual-port memory with an original 2-transistor cell is developed and evaluated for future MAPS chips. Finally, the radiation hardness of the MAPS chips using new available processes is studied, and the future works are prospected.

Quelles sont les particules élémentaires et comment l'univers proviennent sont les principales forces motrices de la physique des hautes énergies. Afin de démontrer le modèle standard et découvrez la nouvelle physique, plusieurs détecteurs sont construits pour les expériences en physique des hautes énergies. Capteurs à pixels CMOS offrent un compromis attirant entre la vitesse de lecture, le budget matériel, la tolérance au rayonnement, la consommation d'énergie et la granularité, par rapport aux capteurs à pixels hybrides et des dispositifs à transfert de charge. Ainsi, les CPS sont un bon choix pour détecter les particules chargées dans les détecteurs de vertex et des télescopes de faisceau. La distribution de puissance devient un enjeu important dans les détecteurs à venir, puisque une quantité considérable de capteurs seront installés. Malheureusement, le «Independent Powering» échoue, comme l'approche traditionnelle. Afin de résoudre les problèmes de distribution de puissance et de fournir des tensions silencieuses, cette thèse se concentre sur la conception de la gestion de l'alimentation à faible bruit, à basse consommation d'énergie, de petite taille et sur-puce pleinement pour les CPS. Les CPS sont d'abord introduits en tirer les exigences de conception de la gestion de l'alimentation. La distribution de puissance dédiées à les CPS est ensuite proposé, dans laquelle la gestion de l'alimentation est utilisée comme seconde étape de conversion de puissance. Deux régulateurs sur-puce pleinement sont proposés pour générer la tension d'alimentation analogique et de la tension d'alimentation de référence requis par l'opération d'échantillonnage double corrélé, respectivement. Deux prototypes ont vérifié ces régulateurs. Ils peuvent répondre aux exigences des CPS. En outre, les techniques de gestion de l'alimentation et de la conception tolérance au rayonnement sont également présentés dans cette thèse. / What are the elementary particles and how did the universe originate are the main driving forces in the high energy physics. In order to further demonstrate the standard model and discover new physics, several detectors are built for the high energy physics experiments. CMOS pixel sensors (CPS) can achieve an attractive tradeoff among many performance parameters, such as readout speed, granularity, material budget, power dissipation, radiation tolerance and integrating readout circuitry on the same substrate, compared with the hybrid pixel sensors and charge coupled devices. Thus, the CPS is a good candidate for tracking the charged particles in vertex detectors and beam telescopes.The power distribution becomes an important issue in the future detectors, since a considerable amount of sensors will be installed. Unfortunately, the independent powering has been proved to fail. In order to solve the power distribution challenges and to provide noiseless voltages, this thesis focuses on the design of a low noise, limited area, low power consumption and full on-chip power management in CPS chips. The CPS are firstly introduced drawing the design requirements of the power management. The power distribution dedicated to CPS chips is then proposed, in which the power management is utilized as the second power conversion stage. Two full on-chip regulators are proposed to generate the analog power supply voltage and the reference voltage required by correlated double sampling operation, respectively. Two prototypes have verified these regulators. They can meet the requirements of CPS. Moreover, the power management techniques and the radiation tolerance design are also presented in this thesis.

Cette thèse est une contribution au document intitulé "Detector Baseline Document (DBD)" décrivant le conceptde détecteur ILD envisagé auprès du collisionneur linéaire international électron-positon ILC (acronyme del'anglais International Linear Collider).Les objectifs de physique de l'ILD nécessitent un détecteur de vertex (VXD) particulièrement léger, rapide et trèsgranulaire permettant d'atteindre une résolution sans précédent sur le paramètre d'impact des trajectoiresreconstruites des particules produites dans les interactions étudiées. Le principal objectif de cette thèse est demontrer comment optimiser les paramètres du VXD dans le cas ou il est composé de Capteurs à Pixels Actifsfabriqués en technologie industrielle CMOS (CAPS). Ce travail a été réalisé en étudiant la sensibilité desperformances d'étiquetage des saveurs lourdes et de la précision sur les rapports d'embranchement hadroniquedu boson de Higgs aux différents paramètres du VXD.Le cahier des charges du VXD, particulièrement ambitieux, a nécessité le développement d'une nouvelletechnologie de capteurs de pixels de silicium, les CAPS, dont le groupe PICSEL de l'IPHC est à l'origine. Lavitesse de lecture et l'influence des paramètres qui régissent la fabrication des capteurs en fonderie ont étéétudiées dans cette thèse, et des prototypesde CAPS ont été caractérisés sur faisceau de particules. Enfin, les performances de trajectométrie d'un VXDcomposé de CAPS a été évalué avec des études de simulation. / This thesis is a contribution to the " Detector Baseline Document ", describing the ILD detector which is intendedfor the International Linear Collider (ILC).The physics goals of the ILD call for a vertex detector (VXD) particularly light, rapid and very granular allowing toreach an unprecedented resolution on the impact parameter of the tracks that reconstruct the particles producedin the studied interactions. The principle goal of this thesis is to show how to optimise the parameters of the VXDin the case that is composed of Active Pixel Sensors manufactured in industrial CMOS technology (CAPS). Thiswork has been realised by studying the sensitivity of the performance of the heavy flavour tagging and theprecision on the hadronic branching fractions of the Higgs boson as a function of different sets of VXDparameters.The specifications of the VXD, particularly ambitious, call for the development of a novel silicon pixel sensorstechnology, the CAPS, which was pioneered by the PICSEL group of IPHC. The readout speed and the influenceof the fabrication parameters have been studied in this thesis, and CAPS prototypes have been characterised intest beams. Finally, the tracking performance of a CAPS based VXD has been evaluated with simulation studies.

Les capteurs monolithiques actifs à pixels (Monolithic Active Pixel Sensors, MAPS) sont de bons candidats pour être utilisés dans des expériences en Physique des Hautes Énergies (PHE) pour la détection des particules chargées. Dans les applications en PHE, des puces MAPS sont placées dans le voisinage immédiat du point d’interaction et sont directement exposées au rayonnement intense de leur environnement. Dans cette thèse, nous avons étudié et amélioré la résistance aux radiations des MAPS. Les effets principaux de l’irradiation et le progrès de la recherche sur les MAPS sont étudiés tout d'abord. Nous avons constaté que les cœurs des SRAM IP incorporées dans la puce MAPS limitent sensiblement la tolérance aux radiations de la puce MAPS entière. Aussi, pour améliorer la radiorésistance des MAPS, trois mémoires radiorésistantes sont conçues et évaluées pour les expériences en PHE. Pour remplacer les cœurs des IP SRAM, une SRAM radiorésistante est développée sur une petite surface. Pour les procédés de plus petit taille de grille des transistors, dans lequel les effets SEU (Single Event Upset) deviennent significatifs, une SRAM radiorésistante avec une tolérance SEU accrue est réalisée à l’aide d’un algorithme de détection et de correction d'erreurs (Error Detection And Correction, EDAC) et un stockage entrelacé des bits. Afin d'obtenir une tolérance aux rayonnements et une densité de micro-circuits plus élevées, une mémoire à double accès avec une cellule à 2 transistors originale est développée et évaluée pour des puces MAPS futures. Enfin, la radiorésistance des puces MAPS avec des nouveaux procédés disponibles est étudiée, et les travaux futurs sont proposés. / Monolithic Active Pixel Sensors (MAPS) are good candidates to be used in High Energy Physics (HEP) experiments for charged particle detection. In the HEP applications, MAPS chips are placed very close to the interaction point and are directly exposed to harsh environmental radiation. This thesis focuses on the study and improvement of the MAPS radiation hardness. The main radiation effects and the research progress of MAPS are studied firstly. During the study, the SRAM IP cores built in MAPS are found limiting the radiation hardness of the whole MAPS chips. Consequently, in order to improve the radiation hardness of MAPS, three radiation hard memories are designed and evaluated for the HEP experiments. In order to replace the SRAM IP cores, a radiation hard SRAM is developed on a very limited area. For smaller feature size processes, in which the single event upset (SEU) effects get significant, a radiation hard SRAM with enhanced SEU tolerance is implemented by an error detection and correction algorithm and a bit-interleaving storage. In order to obtain higher radiation tolerance and higher circuitry density, a dual-port memory with an original 2-transistor cell is developed and evaluated for future MAPS chips. Finally, the radiation hardness of the MAPS chips using new available processes is studied, and the future works are prospected.

What are the elementary particles and how did the universe originate are the main driving forces in the high energy physics. In order to further demonstrate the standard model and discover new physics, several detectors are built for the high energy physics experiments. CMOS pixel sensors (CPS) can achieve an attractive tradeoff among many performance parameters, such as readout speed, granularity, material budget, power dissipation, radiation tolerance and integrating readout circuitry on the same substrate, compared with the hybrid pixel sensors and charge coupled devices. Thus, the CPS is a good candidate for tracking the charged particles in vertex detectors and beam telescopes.The power distribution becomes an important issue in the future detectors, since a considerable amount of sensors will be installed. Unfortunately, the independent powering has been proved to fail. In order to solve the power distribution challenges and to provide noiseless voltages, this thesis focuses on the design of a low noise, limited area, low power consumption and full on-chip power management in CPS chips. The CPS are firstly introduced drawing the design requirements of the power management. The power distribution dedicated to CPS chips is then proposed, in which the power management is utilized as the second power conversion stage. Two full on-chip regulators are proposed to generate the analog power supply voltage and the reference voltage required by correlated double sampling operation, respectively. Two prototypes have verified these regulators. They can meet the requirements of CPS. Moreover, the power management techniques and the radiation tolerance design are also presented in this thesis.

This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

Le sujet de cette thèse est de concevoir un prototype de capteur à pixel CMOS adapté aux couches extérieures du détecteur de vertex de l'International Linear Collider (ILC).Il est le premier prototype de capteur CMOS intégrant un ADC en bas de colonne de 4-bit et une matrice de pixels, dédié aux couches externes. L'architecture du prototype nommé MIMOSA 31 comprend une matrice de pixels de 48 colonnes par 64 lignes, des ADC en bas de colonne. Les pixels sont lus ligne par ligne en mode d'obturation roulant. Les ADCs reçoivent la sortie des pixels en parallèle achève réalisent la conversion en effectuant une approximation de multi-bit/step. Sachant que dans les couches externes de l'ILC, la densité de pixels touchés est de l'ordre de quelques pour mille, !'ADC est conçu pour fonctionner en deux modes (actifs et inactifs) afin de minimiser la consommation d'énergie. Les résultats indiquent que MIMOSA 31 répond aux performances nécessaires pour cette couche de capteurs. / This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.