Neste trabalho o teste de dispositivos analógicos programáveis é abordado. Diversas metodologias de teste analógico existentes são estudadas e algumas delas são utilizadas nas estratégias desenvolvidas. Dois FPAAs (Field Programmable Analog Arrays) comerciais de fabricantes e modelos distintos são utilizados para validar as estratégias de teste propostas. O primeiro dispositivo estudado é um FPAA de tempo contínuo (capaz de implementar circuitos contínuos no tempo) da Lattice Semiconductors. Tal dispositivo é marcado pela característica estrutural de sua programabilidade. Por esta razão, a estratégia a ele aplicada é baseada em um método de teste também estrutural, conhecido como OBT (Oscillation-Based Test). Neste método o circuito é dividido em blocos simples que são transformados em osciladores. Os parâmetros do sinal obtido, tais como a freqüência de oscilação e a amplitude, têm relação direta com os componentes utilizados na implementação do oscilador. Desta maneira, é possível detectar falhas no FPAA observando os parâmetros do sinal gerado. Esta estratégia é estudada inicialmente considerando uma análise externa dos parâmetros do sinal. Como uma alternativa de redução de custos e melhoria na cobertura de falhas, um analisador de resposta baseado em um duplo integrador é adotado, permitindo que a avaliação do sinal gerado pelo oscilador seja feita internamente, utilizando-se os recursos programáveis do próprio FPAA. Os resultados obtidos para as análises interna e externa são então comparados. O segundo FPAA estudado, da Anadigm Company, é um dispositivo a capacitores chaveados que tem como característica a programabilidade funcional. Por esta razão o desenvolvimento de uma técnica de teste estrutural é dificultado, pois não se conhece detalhes da arquitetura do componente. Por esta razão, uma técnica de teste funcional, conhecida como Transient Response Analysis Method, é aplicada ao teste deste FPAA. Neste método o circuito sob teste é dividido em blocos funcionais de primeira e segunda ordem e a resposta transiente destes blocos para um dado estímulo de entrada é analisada. O bloco sob teste é então duplicado e um esquema de auto-teste integrado baseado em redundância é desenvolvido, com o intuito de se obter um sinal de erro. Este sinal de erro representa a diferença das respostas transientes dos blocos duplicados. Como proposta para se aumentar a observabilidade do sinal de erro o mesmo é integrado ao longo tempo, aumentando a capacidade de detecção de falhas quando utilizado este método. Em ambas estratégias o objetivo principal do trabalho é testar os blocos analógicos programáveis dos FPAAs explorando ao máximo a programabilidade dos dispositivos e utilizando recursos pré-existentes para auxiliar no teste. Os resultados obtidos mostram que as estratégias desenvolvidas configuram boas alternativas para o auto-teste integrado deste tipo de componente. / This work addresses the test of programmable analog devices. Several analog test methodologies are studied and some of them are applied in the developed strategies. In order to validate these strategies, two commercial FPAAs (Field Programmable Analog Arrays), of different vendors and distinct models, are considered as devices under test. The first studied device is a continuous-time FPAA from Lattice Semiconductors. One important characteristic of such device is the structural programmability. For this reason the test strategy applied to this FPAA is based in a structural method known as OBT (Oscillation-Based Test). In this method, blocks of the circuit under test are individually converted into oscillators. The parameters of the generated signal, such as the frequency and amplitude, can be expressed as function of the components used in the oscillator implementation. This way, it is possible to detect faults in the FPAA simply observing such parameters. This method is firstly studied considering an external analysis of the signal parameters. However, in a second moment, an internal response analyzer, based on a double integrator, is built with the available programmable resources of the FPAA. This way, overall test cost is reduced, while the fault coverage is increased with no area overhead. The obtained results considering the external analysis and the built-in response evaluation are compared. The second considered FPAA, from Anadigm Company, is a switched capacitor device whose programming characteristic is strictly functional. Thus, a structural test method cannot be easily developed and applied without the previous knowledge of he device architectural details. For this reason, a functional test method known as TRAM (Transient Response Analysis Method) is adopted. In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks for a given input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between the fault-free and faulty Configurable Analog Blocks (CABs). As a proposal to augmenting the observability, the error signal is integrated, enhancing de fault detection capability when using this method. In both developed strategies the main objective is to test the CABs of the FPAAs exploiting the device programmability, using the existing resources in order to aid the test. The obtained results show that the developed strategies represent good alternatives to the built-in self-test of such type of device.

With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also, for a matter of economy of scale, many times a mixed-signal SoC presents a good amount of idle processing power. In such systems it is advantageous to employ more costly digital signal processing provided that it allows a reduction in the analog area demanded or the use of less expensive analog blocks, able to cope with process variations and uncertainty. Besides the technological concerns, other factors that impact the cost of the design also advise to transfer problems from the analog to the digital domain whenever possible: design automation and self-test requirements, for instance. Recent surveys indicate that the total cost in designer hours for the analog blocks of a mixed-signal system can be up to three times the cost of the digital ones. This manuscript explores the concept of bottom-up analog acquisition design, using statistical sampling as a way to reduce the analog area demanded in the design of ADCs within mixed-signal systems. More particularly, it investigates the possibility of using digital modeling and digital compensation of non-idealities to ease the design of ADCs. The work is developed around three axes: the definition of target applications, the development of digital compensation algorithms and the exploration of architectural possibilities. New methods and architectures are defined and validated. The main notions behind the proposal are analyzed and it is shown that the approach is feasible, opening new paths of future research. Keywords:

With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also, for a matter of economy of scale, many times a mixed-signal SoC presents a good amount of idle processing power. In such systems it is advantageous to employ more costly digital signal processing provided that it allows a reduction in the analog area demanded or the use of less expensive analog blocks, able to cope with process variations and uncertainty. Besides the technological concerns, other factors that impact the cost of the design also advise to transfer problems from the analog to the digital domain whenever possible: design automation and self-test requirements, for instance. Recent surveys indicate that the total cost in designer hours for the analog blocks of a mixed-signal system can be up to three times the cost of the digital ones. This manuscript explores the concept of bottom-up analog acquisition design, using statistical sampling as a way to reduce the analog area demanded in the design of ADCs within mixed-signal systems. More particularly, it investigates the possibility of using digital modeling and digital compensation of non-idealities to ease the design of ADCs. The work is developed around three axes: the definition of target applications, the development of digital compensation algorithms and the exploration of architectural possibilities. New methods and architectures are defined and validated. The main notions behind the proposal are analyzed and it is shown that the approach is feasible, opening new paths of future research. Keywords:

Neste trabalho o teste de dispositivos analógicos programáveis é abordado. Diversas metodologias de teste analógico existentes são estudadas e algumas delas são utilizadas nas estratégias desenvolvidas. Dois FPAAs (Field Programmable Analog Arrays) comerciais de fabricantes e modelos distintos são utilizados para validar as estratégias de teste propostas. O primeiro dispositivo estudado é um FPAA de tempo contínuo (capaz de implementar circuitos contínuos no tempo) da Lattice Semiconductors. Tal dispositivo é marcado pela característica estrutural de sua programabilidade. Por esta razão, a estratégia a ele aplicada é baseada em um método de teste também estrutural, conhecido como OBT (Oscillation-Based Test). Neste método o circuito é dividido em blocos simples que são transformados em osciladores. Os parâmetros do sinal obtido, tais como a freqüência de oscilação e a amplitude, têm relação direta com os componentes utilizados na implementação do oscilador. Desta maneira, é possível detectar falhas no FPAA observando os parâmetros do sinal gerado. Esta estratégia é estudada inicialmente considerando uma análise externa dos parâmetros do sinal. Como uma alternativa de redução de custos e melhoria na cobertura de falhas, um analisador de resposta baseado em um duplo integrador é adotado, permitindo que a avaliação do sinal gerado pelo oscilador seja feita internamente, utilizando-se os recursos programáveis do próprio FPAA. Os resultados obtidos para as análises interna e externa são então comparados. O segundo FPAA estudado, da Anadigm Company, é um dispositivo a capacitores chaveados que tem como característica a programabilidade funcional. Por esta razão o desenvolvimento de uma técnica de teste estrutural é dificultado, pois não se conhece detalhes da arquitetura do componente. Por esta razão, uma técnica de teste funcional, conhecida como Transient Response Analysis Method, é aplicada ao teste deste FPAA. Neste método o circuito sob teste é dividido em blocos funcionais de primeira e segunda ordem e a resposta transiente destes blocos para um dado estímulo de entrada é analisada. O bloco sob teste é então duplicado e um esquema de auto-teste integrado baseado em redundância é desenvolvido, com o intuito de se obter um sinal de erro. Este sinal de erro representa a diferença das respostas transientes dos blocos duplicados. Como proposta para se aumentar a observabilidade do sinal de erro o mesmo é integrado ao longo tempo, aumentando a capacidade de detecção de falhas quando utilizado este método. Em ambas estratégias o objetivo principal do trabalho é testar os blocos analógicos programáveis dos FPAAs explorando ao máximo a programabilidade dos dispositivos e utilizando recursos pré-existentes para auxiliar no teste. Os resultados obtidos mostram que as estratégias desenvolvidas configuram boas alternativas para o auto-teste integrado deste tipo de componente. / This work addresses the test of programmable analog devices. Several analog test methodologies are studied and some of them are applied in the developed strategies. In order to validate these strategies, two commercial FPAAs (Field Programmable Analog Arrays), of different vendors and distinct models, are considered as devices under test. The first studied device is a continuous-time FPAA from Lattice Semiconductors. One important characteristic of such device is the structural programmability. For this reason the test strategy applied to this FPAA is based in a structural method known as OBT (Oscillation-Based Test). In this method, blocks of the circuit under test are individually converted into oscillators. The parameters of the generated signal, such as the frequency and amplitude, can be expressed as function of the components used in the oscillator implementation. This way, it is possible to detect faults in the FPAA simply observing such parameters. This method is firstly studied considering an external analysis of the signal parameters. However, in a second moment, an internal response analyzer, based on a double integrator, is built with the available programmable resources of the FPAA. This way, overall test cost is reduced, while the fault coverage is increased with no area overhead. The obtained results considering the external analysis and the built-in response evaluation are compared. The second considered FPAA, from Anadigm Company, is a switched capacitor device whose programming characteristic is strictly functional. Thus, a structural test method cannot be easily developed and applied without the previous knowledge of he device architectural details. For this reason, a functional test method known as TRAM (Transient Response Analysis Method) is adopted. In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks for a given input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between the fault-free and faulty Configurable Analog Blocks (CABs). As a proposal to augmenting the observability, the error signal is integrated, enhancing de fault detection capability when using this method. In both developed strategies the main objective is to test the CABs of the FPAAs exploiting the device programmability, using the existing resources in order to aid the test. The obtained results show that the developed strategies represent good alternatives to the built-in self-test of such type of device.

Neste trabalho o teste de dispositivos analógicos programáveis é abordado. Diversas metodologias de teste analógico existentes são estudadas e algumas delas são utilizadas nas estratégias desenvolvidas. Dois FPAAs (Field Programmable Analog Arrays) comerciais de fabricantes e modelos distintos são utilizados para validar as estratégias de teste propostas. O primeiro dispositivo estudado é um FPAA de tempo contínuo (capaz de implementar circuitos contínuos no tempo) da Lattice Semiconductors. Tal dispositivo é marcado pela característica estrutural de sua programabilidade. Por esta razão, a estratégia a ele aplicada é baseada em um método de teste também estrutural, conhecido como OBT (Oscillation-Based Test). Neste método o circuito é dividido em blocos simples que são transformados em osciladores. Os parâmetros do sinal obtido, tais como a freqüência de oscilação e a amplitude, têm relação direta com os componentes utilizados na implementação do oscilador. Desta maneira, é possível detectar falhas no FPAA observando os parâmetros do sinal gerado. Esta estratégia é estudada inicialmente considerando uma análise externa dos parâmetros do sinal. Como uma alternativa de redução de custos e melhoria na cobertura de falhas, um analisador de resposta baseado em um duplo integrador é adotado, permitindo que a avaliação do sinal gerado pelo oscilador seja feita internamente, utilizando-se os recursos programáveis do próprio FPAA. Os resultados obtidos para as análises interna e externa são então comparados. O segundo FPAA estudado, da Anadigm Company, é um dispositivo a capacitores chaveados que tem como característica a programabilidade funcional. Por esta razão o desenvolvimento de uma técnica de teste estrutural é dificultado, pois não se conhece detalhes da arquitetura do componente. Por esta razão, uma técnica de teste funcional, conhecida como Transient Response Analysis Method, é aplicada ao teste deste FPAA. Neste método o circuito sob teste é dividido em blocos funcionais de primeira e segunda ordem e a resposta transiente destes blocos para um dado estímulo de entrada é analisada. O bloco sob teste é então duplicado e um esquema de auto-teste integrado baseado em redundância é desenvolvido, com o intuito de se obter um sinal de erro. Este sinal de erro representa a diferença das respostas transientes dos blocos duplicados. Como proposta para se aumentar a observabilidade do sinal de erro o mesmo é integrado ao longo tempo, aumentando a capacidade de detecção de falhas quando utilizado este método. Em ambas estratégias o objetivo principal do trabalho é testar os blocos analógicos programáveis dos FPAAs explorando ao máximo a programabilidade dos dispositivos e utilizando recursos pré-existentes para auxiliar no teste. Os resultados obtidos mostram que as estratégias desenvolvidas configuram boas alternativas para o auto-teste integrado deste tipo de componente. / This work addresses the test of programmable analog devices. Several analog test methodologies are studied and some of them are applied in the developed strategies. In order to validate these strategies, two commercial FPAAs (Field Programmable Analog Arrays), of different vendors and distinct models, are considered as devices under test. The first studied device is a continuous-time FPAA from Lattice Semiconductors. One important characteristic of such device is the structural programmability. For this reason the test strategy applied to this FPAA is based in a structural method known as OBT (Oscillation-Based Test). In this method, blocks of the circuit under test are individually converted into oscillators. The parameters of the generated signal, such as the frequency and amplitude, can be expressed as function of the components used in the oscillator implementation. This way, it is possible to detect faults in the FPAA simply observing such parameters. This method is firstly studied considering an external analysis of the signal parameters. However, in a second moment, an internal response analyzer, based on a double integrator, is built with the available programmable resources of the FPAA. This way, overall test cost is reduced, while the fault coverage is increased with no area overhead. The obtained results considering the external analysis and the built-in response evaluation are compared. The second considered FPAA, from Anadigm Company, is a switched capacitor device whose programming characteristic is strictly functional. Thus, a structural test method cannot be easily developed and applied without the previous knowledge of he device architectural details. For this reason, a functional test method known as TRAM (Transient Response Analysis Method) is adopted. In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks for a given input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between the fault-free and faulty Configurable Analog Blocks (CABs). As a proposal to augmenting the observability, the error signal is integrated, enhancing de fault detection capability when using this method. In both developed strategies the main objective is to test the CABs of the FPAAs exploiting the device programmability, using the existing resources in order to aid the test. The obtained results show that the developed strategies represent good alternatives to the built-in self-test of such type of device.

With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also, for a matter of economy of scale, many times a mixed-signal SoC presents a good amount of idle processing power. In such systems it is advantageous to employ more costly digital signal processing provided that it allows a reduction in the analog area demanded or the use of less expensive analog blocks, able to cope with process variations and uncertainty. Besides the technological concerns, other factors that impact the cost of the design also advise to transfer problems from the analog to the digital domain whenever possible: design automation and self-test requirements, for instance. Recent surveys indicate that the total cost in designer hours for the analog blocks of a mixed-signal system can be up to three times the cost of the digital ones. This manuscript explores the concept of bottom-up analog acquisition design, using statistical sampling as a way to reduce the analog area demanded in the design of ADCs within mixed-signal systems. More particularly, it investigates the possibility of using digital modeling and digital compensation of non-idealities to ease the design of ADCs. The work is developed around three axes: the definition of target applications, the development of digital compensation algorithms and the exploration of architectural possibilities. New methods and architectures are defined and validated. The main notions behind the proposal are analyzed and it is shown that the approach is feasible, opening new paths of future research. Keywords:

A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis. With technology scaling, the inverter switching times are becoming shorter thus leading to better resolution of edges in time. This time resolution is observed to be superior to voltage resolution in the face of reducing supply voltage and increasing variations as physical dimensions shrink. In this thesis, a new method of observability of analog signals is proposed, which is digital-friendly and scalable to future deep sub-micron (DSM) processes. The low-bandwidth analog test voltage is captured as the delay between a pair of clock signals. The delay thus setup is measured digitally in accordance with the desired resolution. Such an approach lends itself easily to distributed manner, where the routing of analog signals over long paths is minimized. A small piece of circuitry, called sampling head (SpH) placed near each test voltage, acts as a transducer converting the test voltage to a delay between a pair of low-frequency clocks. A probe clock and a sampling clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node consists of a pair of delay cells and a pair of flip-flops, giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. The concept is validated by designing a test chip in UMC 130 nm CMOS process. Sub-mV accuracy for static signals is demonstrated for a measurement time of few milliseconds and ENOB of 5.29 is demonstrated for low bandwidth signals in the absence of sample-and-hold circuitry. The sampling clock is derived from the probe clock using a PLL and the design equations are worked out for optimal performance. To validate the concept, the duty-cycle of the probe clock, whose ON-time is modulated by a sine wave, is measured by the same DMU. Measurement results from FPGA implementation confirm 9 bits of resolution.