Since digital system has become very common today it is important to have good interfaces in between the analog and digital domain. This puts high demandson the analog to digital converter. It is therefore important in the design of theanalog to digital converter to reduce noise and offset as much as possible. That isalso what this analysis is going to consider but in a comparator which is a crucialpart of the analog to digital converter. The comparator consists of a preamplifierand a latch and it is the preamplifier that will be studied here. The analog todigital converter in consider is of PSAR structure. Some other structures will alsobe mentioned in the first part together with some noise theory.

<p>Since digital system has become very common today it is important to have good interfaces in between the analog and digital domain. This puts high demandson the analog to digital converter. It is therefore important in the design of theanalog to digital converter to reduce noise and offset as much as possible. That isalso what this analysis is going to consider but in a comparator which is a crucialpart of the analog to digital converter. The comparator consists of a preamplifierand a latch and it is the preamplifier that will be studied here. The analog todigital converter in consider is of PSAR structure. Some other structures will alsobe mentioned in the first part together with some noise theory.</p><p> </p><p> </p>

CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on "split ADC" architecture. Each of the two split channels, ADC "A" and "B", contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs' sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADC’s LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate).

As neural interfaces continue to progress toward practical applications, there is increased demand for smaller, more efficient and cost effective devices. Event related potentials (ERPs) have recently been demonstrated to be reliable for practical communication in disabled individuals using the P300 Speller paradigm. With the objective of simplifying the processing of ERPs in order to minimize the hardware/computational requirements, and therefore the power consumption (for increased battery life for wireless, etc.), this study examines the effects of the analog-to-digital converter amplitude quantization on the ERP classification accuracy for the P300 Speller.

No description available.

The demand for efficient and reliable high rate communication is ever increasing. In this thesis we study different challenges in such systems, and their possible solutions. A goal for many years has been to implement as much as possible of a radio system in the digital domain, the ultimate goal being so called software defined radio (SDR) where the inner workings of a radio standard can be changed completely by changing the software. One important part of an SDR receiver is the high speed analog-to-digital converter (ADC) and one path to reach this high speed is to use a number of parallel, time-interleaved, ADCs. Such ADCs are, however, sensitive to sampling instant offsets, DC level offsets and gain offsets. This thesis discusses estimators based on fractional-delay filters and one application of these estimmators is to estimate and calibrate the relative delay, gain, and DC level offset between the ADCs comprising the time interleaved ADC. In this thesis we also present a technique for carrier frequency offset (CFO) estimation in orthogonal frequency division multiplexing (OFDM) systems. OFDM has gone from a promising digital radio transmission technique to become a mainstream technique used in several current and future standards. The main attractive property of OFDM is that it is inherently resilient to multipath reflections because of its long symbol time. However, this comes at the cost of a relatively high sensitivity to CFO. The proposed estimator is based on locating the spectral minimas within so-called null or virtual subcarriers embedded in the spectrum.~The spectral minimas are found iteratively over a number of symbols and is therefore mainly useful for frequency offset tracking or in systems where an estimate is not immediately required, such as in TV or radio broadcasting systems. However, complexity-wise the estimator is relatively easy to implement and it does not need any extra redundancy beside a nonmodulated subcarrier. The estimator performance is studied both in a channel with additive white Gaussian noise and in a multipath frequency selective channel environment. Interpolators and decimators are an important part of many systems, e.g. radio systems, audio systems etc. Such interpolation (decimation) is often performed using cascaded interpolators (decimators) to reduce the speed requirements in different parts of the system. In a fixed-point implementation, scaling is needed to maximize the use of the available word lengths and to prevent overflow. In the final part of the thesis, we present a method for scaling of multistage interpolators/decimators using multirate signal processing techniques. We also present a technique to estimate the output roundoff noise caused by the internal quantization.

<p>In order to perform the production testing of the video quality of manufactured set-top-boxes for digital television, an FPGA-based measurement system is designed. Background on sampling and video signals are given, as well as the requirements given by Motorola. From this, a design is proposed and implemented. The demonstrator works as planned and shows good performance in regards to signal to noise ratio and differential gain. The implemented digital communication protocols, such as USB and I2C, also work as expected.</p><p>The main conclusion from this thesis is that implementing video test systems using FPGA is a good approach offering many advantages compared to commercial video measurement instruments or plug-in cards for PCs.</p>

In order to perform the production testing of the video quality of manufactured set-top-boxes for digital television, an FPGA-based measurement system is designed. Background on sampling and video signals are given, as well as the requirements given by Motorola. From this, a design is proposed and implemented. The demonstrator works as planned and shows good performance in regards to signal to noise ratio and differential gain. The implemented digital communication protocols, such as USB and I2C, also work as expected. The main conclusion from this thesis is that implementing video test systems using FPGA is a good approach offering many advantages compared to commercial video measurement instruments or plug-in cards for PCs.

No description available.

In many developing countries health care conditions are poor and there is a lack of healthcare professionals and diagnostics tools. Cheap and easy-to-use diagnostics tools have been developed to make practicing medicine easier under these conditions. However, signal monitors can be many and spread out, making it hard for the limited number of medical workers to handle. The monitors are also stationary, making mobile supervision impossible. In this thesis a solution is suggested, made of a hardware setup consisting of an Arduino UNO and Bluetooth module paired with an application, capable of analog to digital conversion, wireless transfer and display of medical signals. Furthermore, two different QRS detection algorithms are tested, a larger and accurate model called Pan-Tompkins and a smaller and faster, moving average based filtering system. The transmission circuit as well as the signal displayed showed promise. However, the analog to digital conversion was noisy due to the power source. The tested algorithms showed that speed and low computational requirements are traded for precision.