Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquence. / This thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation.

Les technologies CMOS représentent aujourd’hui plus de 90% du marché des capteurs d’images : elles permettent d’intégrer des systèmes intelligents dans une seule puce (SoC = System-On-Chip) et ouvrent la voie à l’intégration d’algorithmes de plus en plus complexes dans les dernières générations de capteurs. Des techniques telles que la reconstruction grande dynamique nécessitent d’acquérir plusieurs images avec un même capteur et de les recombiner. Ces nouvelles contraintes nécessitent d’augmenter drastiquement le débit d’images pour des capteurs de tailles conséquentes (Jusqu'à 30 Mpixels), ainsi que d’augmenter la résolution du convertisseur analogique numérique (jusqu’à 14 bits). Cela crée une demande forte en techniques de conversion analogique-numérique. Ces techniques doivent obéir en même temps aux contraintes de performance notamment la vitesse, la résolution, le faible bruit, la faible consommation et l'intégrabilité mais aussi aux contraintes de qualité d'image impactées directement par la chaine de conversion analogique-numérique en plus de la technologie du pixel. D'ici découle une double problématique pour le sujet:- Etudier et déterminer les limites atteignables en termes de performance sur les différents axes précités.- Gestion du fonctionnement massivement parallèle lié à la structure inhérente des capteurs d'image en vue d'avoir une qualité d'image irréprochable. / CMOS technologies represent nowadays more than 90% of image sensors market given their features namely the possibility of integrating entire intelligent systems on the same chip (SoC = System-On-Chip). Thereby, allowing the implementation of more and more complex algorithms in the new generations of image sensors.New techniques have emerged like high dynamic range reconstruction which requires the acquisition of several images to build up one, thus multiplying the frame rate.These new constraints require a drastic increase of image rate for sensors ofconsiderable size (Up to 30 Mpix and more). At the same time, the ADCresolution has to be increased to be able to extract more details (until 14 bits).With all these demanding specifications, analog-to-digital conversion capabilities have to be boosted as far as possible.These capabilities can be distinguished into two main research axes representing the pillars of the PhD work, namely:+ The study of the reachable limits in terms of performance: Speed, Resolution,Low Noise, Low power consumption and small design pitch.+ The management of the highly parallel operation linked to the structure of animage sensor. Solutions have to be found so as to avoid image artefacts andpreserve the image quality.

Made available in DSpace on 2016-08-17T14:53:14Z (GMT). No. of bitstreams: 1 Rafael Oliveira Nunes.pdf: 2514852 bytes, checksum: 72d45d30f5d3d54f97f6401ca5005607 (MD5) Previous issue date: 2010-12-23 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Programmable integrated circuits for specified applications enable its adjustment after fabrication, to fit more than one application within a certain set of applications. These circuits are flexible, but could lose in performance when compared to other circuit constructed to serve only a specific application. A programmable system can be applied to measurements involving a set of sensors with different characteristics of signals and an analog-to-digital converter. The signal range for each sensor should be adjusted as close to the input range of analog-digital converter as possible, to ensure the measurement with the full range of the signal. A solution for ensure the adjustable ranges is the employ a measurement system with programmable conditioning circuit. In this work, an analog-to-digital converter with adjustable input range is proposed, providing, equivalently, an adjustable gain value to the analog input signal. The gain values compose a minimum set to ensure no loss of measurement range of the signal, with loss of resolution within an acceptable limit. The proposed converter is a discrete integrator type with switched capacitor circuits. Behavioral and SPICE simulations were performed to validate the proposed converter. / Circuitos integrados programáveis possibilitam o seu ajuste após a fabricação, para se adequar a mais de uma aplicação dentro de um conjunto determinado de aplicações. Esses circuitos são flexíveis, mas podem perder em desempenho quando comparado a outro circuito fabricado para servir a apenas uma aplicação específica. Um sistema programável pode ser aplicado em medições que envolvam um conjunto de sensores com características diferentes de sinais e um conversor analógico-digital. A faixa de sinal em cada sensor deve ser ajustada o mais próximo da faixa de entrada do conversor analógico-digital, para garantir a medição com a faixa completa do sinal. Uma solução para garantir o ajuste das faixas é o uso de um sistema de medição com circuito de condicionamento programável. Neste trabalho, um conversor analógico-digital com faixa de entrada ajustável é proposto, proporcionando, de forma equivalente, um valor de ganho ajustável ao sinal analógico de entrada. Os valores de ajuste pertencem a um conjunto mínimo de ganhos definidos para garantir que não haja perda da faixa de medição do sinal, com perda de resolução dentro de um limite aceitável. O conversor proposto é do tipo integrador discreto com circuitos a capacitor chaveado. Simulações comportamentais e em SPICE foram realizadas de forma a validar o conversor proposto.

To explore spectral opportunities in wideband regime for cognitive radio we need a wideband spectrum sensing receiver. Current wideband receiver architectures need wideband analog to digital converter (ADC) to sample wideband signal. As current state-of-art ADC has limitation in terms of power and sampling rate, we need to explore some alternative solutions. Compressive sampling (CS) data acquisition method is one of the solutions. Cognitive Radio signal, which is sparse in frequency domain can be sampled at Sub-Nyquist rate using low rate ADC. To relax the receiver complexity in terms of performance requirement we can use Modulated Wideband Converter (MWC) architecture, a Sub-Nyquist sampling method. In this thesis circuit design of this architecture covers signal within a frequency range of 500 MHz to 2.1 GHz, with a channel bandwidth of 1600 MHz. By using 8 parallel lines with channel trading factor of 11, effective sampling rate of 550 MHz is achieved for successful support recovery of multi-band input signal of size N=12.

A data acquisition system (DAQ) was designed based on the use of a STM32 microcontroller. Its purpose is to provide a transparent and low-cost alternative to commercially available DAQs, providing educators a means to teach students about the process through which data are collected as well as the uses of collected data. The DAQ was designed to collect data from rotating machinery spinning at a speed up to 10,000 RPM and send this data to a computer through a USB 2.0 full-speed connection. Multitasking code was written for the DAQ to allow for data to be simultaneously collected and transferred over USB. Additionally, a console application was created to control the DAQ and read data, and MATLAB code written to analyze the data. The DAQ was compared against a custom assembled National Instruments CompactDAQ system. Using a Bentley-Nevada RK 4 Rotor Kit, data was simultaneously collected using both DAQs. Analysis of this data shows the capabilities and limitations of the low cost DAQ compared to the custom CompactDAQ.

In this work is designed programme unit for acquisition analog acoustic signlas from sensors. There is used accurate A/D converter ADS1287 by the company Texas Iinstrument with resolution of 24 bits to digitizing these signals. There is used 32-bit microprocessor AT91SAM7S64 by the company Atmel to control this A/D converter and sending digitized data to PC. This microprocessor has implemented USB interface. By force of developmental programme units whit microprocessor and A/D converter is produced programme for microprocessor in developmental setting IAR Embedded Workbench IDE 5.0 and simple aplication for PC in setting Borland C++ Builder. Both of those programs are in language C++. Rate of sampling is 26 kHz. On the basis is realized programme unit USB-ADC whit microprocessor and A/D converter.

Diploma thesis handles with set up of peripheral modules of the processor TC275 families’ AURIX developed by Infineon. Processor’s peripheral module QSPI implements communication SPI set up as master on a bus supported by another processor’s module DMA. Module DMA periodically service transmit and receive shift buffers of QSPI which are connected with slave analog to digital converter IC CIC751. Another peripheral module is MultiCAN. Programmed drivers used only basic header files with register definition of processor TC275, which are part of IDE TriCore Free Entry Tool Chain used for created drivers.

The diploma thesis deals with the design of a programmable load. As first, the research of available commercial devices was made in the theoretical part. Based on this research, the design possibilities of programmable load were discussed. As next, the design of resistor network was made, using a computer program that was developed for this purpose. Practical part deals with a realization of module of load, control board and software development. Proposed system consists of control board and ten modules. Modules have floating input terminals. This approach facilitate to arbitrary combination of their inputs. Modules are designed to work with DC and AC power supplies.

Diplom work describes a proposal and the design of the device for controlling the temperature test in a climatic chamber Heraeus and the creation of software for operating equipment. Work describes in detail the design and construction interface for the climate chamber, with which will be able to run automated test sequences and the development of the firmware and the operating software to start the temperature test.

High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW. The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW. A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done. / <p>Report code: LiU-Tek-Lic-2005:68.</p>