This thesis presents two methods that enable high internal quantizer resolution in delta-sigma analog-to-digital converters. Increasing the quantizer resolution in a delta-sigma modulator can increase SNR, improve stability and reduce integrator power consumption. However, each added bit of quantizer resolution also causes an exponential increase in the power dissipation, required area and complexity of the dynamic element matching (DEM) circuit required to attenuate digital-to-analog converter (DAC) mismatch errors. One way to overcome these drawbacks is to segment the feedback signal, creating a "coarse" signal and a "fine" signal. This reduces the DEM circuit complexity, power dissipation, and size. However, it also creates additional problems. The negative consequences of segmentation are presented, along with two potential solutions: one that uses calibration to cancel mismatch between the "coarse" DAC and the "fine" DAC, and another that frequency-shapes this mismatch error. Mathematical analysis and behavioral simulation results are presented. A potential circuit design for the frequency-shaping method is presented in detail. Circuit simulations for one of the proposed implementations show that the delay through the digital path is under 7 ns, thus permitting a 50 MHz clock frequency for the overall ADC.

Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm

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Impulse Ultra Wideband (UWB) communications is an emerging technology that promises a number of benefits over traditional narrowband or broadband signals: extremely high data rates, extremely robust operation in dense multipath environments, low probability of intercept/detection, and the ability to operate concurrently with existing users. Unfortunately, most currently available UWB systems are based on dedicated hardware, preventing researchers from investigating algorithms or architectures that take advantage of some of the unique properties of UWB signals. This dissertation outlines the development of a general purpose software radio transceiver testbed for UWB signals. The testbed is an enabling technology that provides a development platform for investigating ultra wideband communication algorithms (e.g., acquisition, synchronization, modulation, multiple access), ranging or radar (e.g., precision position location, intrusion detection, heart and respiration rate monitoring), and could potentially be used in the area of ultra wideband based medical imaging or vital signs monitoring. As research into impulse ultra wideband expands, the need is greater now than ever for a platform that will allow researchers to collect real-world performance data to corroborate theoretical and simulation results. Additionally, this dissertation outlines the development of the Time-Interleaved Analog to Digital Converter array which served as the core of the testbed, along with a comprehensive theoretical and simulation-based analysis on the effects of Analog to Digital Converter mismatches in a Time-Interleaved Sampling array when the input signal is an ultra wideband Gaussian Monocycle. Included in the discussion is a thorough overview of the implementation of both a scaled-down prototype as well as the final version of the testbed. This dissertation concludes by evaluating the of the transceiver testbed in terms of the narrowband dynamic range, the accuracy with which it can sample and reconstruct a UWB pulse, and the bit error rate performance of the overall system. / Ph. D.

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for electronic store cord neural signals from many neurons. The continuous increase in demand of data from more number of neurons is challenging for the design of an efficient neural recording frontend(NRFE). Power consumption per channel and data rate minimization are two key problems which need to be addressed by next generation of neural recording systems. Area consumption per channel must be low for small implant size. Dynamic range in NRFE can vary with time due to change in electrode-neuron distance or background noise which demands adaptability. In this thesis, techniques to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and architectures, are proposed. An area efficient low power neural LNA is presented in UMC 0.13 μm 1P8M CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 μA , modulating input referred noise from 9.92 μV to 3.9μV . We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier. It obviates the need of large input coupling capacitance in the amplifier which saves considerable amount of chip area. In vitro experiments were performed to validate the applicability of the neural LNA in neural recording systems. ADC is another important block in a NRFE. An 8-bit SAR ADC along with the input and reference buffer is implemented in 0.13 μm CMOS technology. The use of ping-pong input sampling is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the output data rate, the A/D process is only enabled through a proposed activity dependent A/D scheme which ensures that the background noise is not processed. Based on the dynamic range requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce power consumption linearly. The ADC consumes 8.8 μW from1Vsupply at1MS/s and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13 μm CMOS technology. Power consumption in SARADCs is greatly benefited by CMOS scaling due to its highly digital nature. However the power consumption in the capacitive DAC does not scale as well as the digital logic. In this thesis, two energy-efficient DAC switching techniques, Flip DAC and Quaternary capacitor switching, are proposed to reduce their energy consumption. Using these techniques, the energy consumption in the DAC can be reduced by 37 % and 42.5 % compared to the present state-of-the-art. A novel concept of code-independent energy consumption is introduced and emphasized. It mitigates energy consumption degradation with small input signal dynamic range.

Abstract The goal of this dissertation was to study and model the settling transient response of switched-capacitor (SC) circuit, which is the most important building block of Analog-to-Digital converters (ADCs), and to improve the settling performance of the SC circuit implemented in ADC in CMOS technology. In the design of the SC circuit, there are common obstacles in obtaining a precise and fast settling with low power consumption. The main contribution of this thesis is to speed up different SC circuits without adding extra power consumption or to achieve the required settling precision with low power consumption. Two solutions to reduce the power consumption of SC integrators in sigma-delta (SD) ADCs were designed and verified by simulations. These implementations are based on the passive charge redistribution technique by injecting a precalculated open-loop charge in the output of the first integrator. The injected charge was implemented either by a continuous function of the input and feedback voltages or by quantizing to three levels. In both cases, the idea is to minimize the initial transient voltage in the input of the first OTA and hence bypass the slewing of the OTA. Another approach was proposed for the traditional SC residue circuit of the pipeline ADC, where a load capacitor is connected to the output during the evaluation phase. Here, a pre-charge of the load capacitance can be used. One proposed implementation is called the continuously controlled pre-charged technique. It pre-charges the load capacitor to the proper voltage during the previous phase, connects the pre-charged load capacitor to the output of the OTA during the evaluation phase, and hence pulls the charge sharing so that the initial input step of the OTA is instantaneously minimized. The other implementation called the minimal pre-charged method implemented for the SC residue circuit of the pipeline ADC is to simply pre-charge the load capacitor with the fixed existing voltage, minimized the spread of the initial input voltage. This proposed technique did not require any additional active components. / Tiivistelmä Kytkettyihin kapasitansseihin (SC-tekniikka) perustuvat vahvistimet ovat CMOS-tekniikkaan perustuvien analogia-digitaalimuuntimien (AD-muunnin) tärkeimpiä osia. Tämän väitöstyön tavoitteena oli tutkia ja mallittaa SC-tekniikkaan perustuvien vahvistinpiirien asettumisaikaa, ja etsiä piiriteknisiä keinoja asettumisajan nopeuttamiseksi. SC-piirien suunnittelun suurimpia ongelmia on saavuttaa tarkka ja nopea asettuminen mahdollisimman pienellä tehonkulutuksella. Tämän työn päätuloksina on joukko keinoja, joilla voidaan nopeuttaa SC-kytkettyjen vahvistimien asettumista ilman että niiden tehonkulutusta lisätään, tai saavuttaa aiempi suorituskyky pienemmällä tehonkulutuksella. Menetelmät perustuvat siihen, että SC-piirin passiivista varausjakautumista ohjataan niin, että vahvistimen tulosolmussa oleva transientti minimoituu, jolloin vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelle, vaan sen asettuminen nopeutuu merkittävästi. Sigma-delta-tyyppiset AD-muuntimet koostuvat SC-integraattoreista, ja näiden asettumisen nopeuttamiseen kehitettiin ja varmennettiin simuloiden kaksi tapaa. Varauksen jakautumista autettiin syöttämällä erillisellä varauspumpulla transkonduktanssivahvistimen lähtösolmuun tietty, integraattorin tilasta ja tuloista riippuva varaus. Tällöin vahvistimen tulossa näkyvä alkutransientti pienenee, ja vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelleen, jolloin sen asettumisvirhe pienenee merkittävästi. Varausinjektio toteutettiin kahdella eri tavalla: laskemalla tarvittava varaus joko jatkuvana funktiona tulosignaaleista, tai approksimoimalla sitä muutamalla diskreetillä tasolla. Pipeline-tyyppisissä AD-muuntimissa peruslohko koostuu SC-kytketystä vahvistimesta, jonka kuormakapasitanssi on kytkettynä vahvistimen lähtöön asettumisen aikana. Tämän kapasitanssin esivaraaminen sopivasti tarjoaa hyvin yksinkertaisen keinon ohjata varausjakautumista niin, että vahvistimen tulossa oleva transientti saadaan minimoitua ja toiminta virtarajoitteisessa moodissa vältettyä. Tässäkin tapauksessa kehitettiin ja varmennettiin kaksi vaihtoehtoista toteutusta. Ensimmäisessä kuormakapasitanssin esivarausjännite lasketaan tulosuureiden jatkuvana funktiona erillisellä summausvahvistimella. Toisessa, hyvin minimalistisessa ratkaisussa esivaraukseen käytetään kolmea käytettävissä olevaa kiinteää jännitettä. Tämä menetelmä ei vaadi lainkaan ylimääräisiä aktiivikomponentteja.

Multiple-input multiple-output (MIMO) radars, which utilize multiple transmitters and receivers to send and receive independent waveforms, have been actively investigated as a next generation radar technology inspired by MIMO techniques in communication theory. Complementary metal-oxide-semiconductor (CMOS) technology offers an opportunity for dramatic cost and size reduction for a MIMO array. However, the resulting formidable signal processing burden has not been addressed properly and remains a challenge. On the other hand, from a block-level point of view, an analog-to-digital converter (ADC) is required for mixed-signal processing to convert analog signals to digital signals, but an ADC occupies a significant portion of a system's budget. Therefore, improvement of an ADC will greatly enhance various trade-offs. This research presents an alternative and viable approach for a MIMO array from a system architecture point of view, and also develops circuit level improvement techniques for an ADC. This dissertation presents a fully-integrated analog pulse compressor (APC) based on an analog matched filter in a mixed signal domain as a key block for the waveform diversity MIMO radar. The performance gain of the proposed system is mathematically presented, and the proposed system is successfully implemented and demonstrated from the block level to the system level using various waveforms. Various figures of merit are proposed to aid system evaluations. This dissertation also presents a low-power ADC based on an asynchronous sample-and-hold multiplying SAR (ASHMSAR) with an enhanced input range dynamic comparator as a key element of a future system. Overall, with the new ADC, a high level of system performance without severe penalty on power consumption is expected. The research in this dissertation provides low-cost and low-power MIMO solutions for a future system by addressing both system issues and circuit issues comprehensively.

The motivation behind this work is to target the demand for high-speed medium-resolution ADCs for satellite communication systems. An 8-bit, 12.5GS/s folding-interpolating ADC was designed in 0.25µm, 190GHz SiGe BiCMOS technology from IHP. The ADC consists of a THA, a reference resistor ladder, folding amplifiers, an interpolating resistor string, a comparator array, a digital encoder, a coarse quantizer and a bit synchronizer. Post-layout simulation results of the ADC verify that its performance meets all the required specifications. By comparison to other high-speed ADCs, implemented in SiGe technologies, the present design features the highest sampling rate for 8-bit resolution ADCs to date with a good FOM (12.9pJ/conversion). The THA and the comparator were implemented experimentally and characterized to verify their performance and to ascertain the possibility of implementing the complete ADC. The experimental results meet the expected specifications and indicate that both circuits are suitable for the implementation of the ADC.

Une nouvelle méthode de test pour les convertisseurs ADC et DAC embarqués dans un système complexe a été développée en prenant en compte les nouvelles contraintes affectant le test. Ces contraintes, dues aux tendances de design de systèmes, sont un nombre réduit de point d'accès aux entrées/sorties des blocs analogiques du système et une augmentation galopante du nombre et des performances des convertisseurs intégrés. La méthode proposée consiste à connecter les convertisseurs DAC et ADC dans le domaine analogique pour n'avoir besoin que d'instruments de test numériques pour générer et capturer les signaux de test. Un algorithme de traitement du signal a été développé pour discriminer les erreurs des DACs et ADCs. Cet algorithme a été validé par simulation et par expérimentation sur des produits commercialisés par NXP. La dernière partie de la thèse a consisté à développer de nouvelles applications pour l'algorithme.

The motivation behind this work is to target the demand for high-speed medium-resolution ADCs for satellite communication systems. An 8-bit, 12.5GS/s folding-interpolating ADC was designed in 0.25µm, 190GHz SiGe BiCMOS technology from IHP. The ADC consists of a THA, a reference resistor ladder, folding amplifiers, an interpolating resistor string, a comparator array, a digital encoder, a coarse quantizer and a bit synchronizer. Post-layout simulation results of the ADC verify that its performance meets all the required specifications. By comparison to other high-speed ADCs, implemented in SiGe technologies, the present design features the highest sampling rate for 8-bit resolution ADCs to date with a good FOM (12.9pJ/conversion). The THA and the comparator were implemented experimentally and characterized to verify their performance and to ascertain the possibility of implementing the complete ADC. The experimental results meet the expected specifications and indicate that both circuits are suitable for the implementation of the ADC.