Delta sigma data converters have found to be of greater interest for almost 40 years now. Continuous time implementation of these converters, especially for high speed and low power applications has been very challenging. Here in this thesis we have discussed Resistor Capacitor (RC) implementation of Chebyshev Type II high pass Noise Transfer Function (NTF). RC implementation has its own advantages compared to that of a Switched Capacitor (SC) circuit. While SC implementation has the advantages of being discrete-time, no resistors used, and improved stability control, RC implementation has the advantage of no switches being used (other than the quantizer) and therefore a simpler circuit implementation. In this thesis the details of the design and analysis of a fourth order RC delta sigma data converter will be given. The NTF is that of a fourth-order Chebyshev Type II highpass filter, where the noise is high passed and removed using a low pass filter and the signal remains constant across the low frequency band. The circuit implementation consists of four RC integrators with gain stages that are determined from the desired transfer function. The feedback loop includes of a sample and hold circuit followed by a one-bit quantizer: these are the only nonlinear elements in the circuit design. The circuit design procedure will be given, starting with the desired NTF characteristics, and yielding the required gain parameters for the four integrator circuit architecture, obtained to implement the requiredH(s). MATLAB is used for easy computation. The circuit simulation, yielding the bit stream frequency spectrum and the signal to noise ratio, will be based on Mentor Graphics Eldo SPICE simulations. The overall performance achieves the equivalent of 11 bits. This is obtained from a fourth order circuit, using RC implementation. / Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering. / Includes bibliographical references (leaves 37-38) / "December 2006."

This thesis presents two hybrid luminescence-based biochemical photosensory microsystems: a CMOS/microfluidic chemiluminescence contact imager, and a CMOS/thin-film fluorescence contact imager. A compact, low-power analog-to-digital converter (ADC) architecture for use in such sensory microsystems is also proposed. Both microsystems are prototyped in a standard 0.35um CMOS technology. The CMOS/microfluidic microsystem integrates a 64x128-pixel CMOS imager and a soft polymer microfluidic network. Circuit techniques are employed to reduce the dark current and circuit noise for low-level light sensitivity. Experimental validation is performed by detecting luminol chemiluminescence and electrochemiluminescence. The CMOS/thin-film microsystem integrates an existing 128x128-pixel CMOS imager and a prefabricated, high-performance optical filter. Experimental validation is performed by detecting human DNA labeled with Cyanine-3 fluorescent dye. The proposed ADC architecture employs a novel digital-to-analog converter with a flexible trade-off between the integration area and the conversion speed. The area savings and good linearity of the DAC are verified by simulations.

In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from Jan. 7, 2013 - Jan. 7, 2014

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

This dissertation presents a comprehensive design and analysis framework for system-on-a-chip analog-to-digital conversion design. The design encompasses a broad class of systems, which take advantage of system-on-a-chip complexity. This class is exemplified by an interferometric photodetector array based bio-optoelectronic sensor that is built and tested as part of the reported work. While there have been many discussions of the technical details of individual analog-to-digital converter (ADC) schemes in the literature, the importance of the analog front-end as a pre-processor for a data converter and the generalized analysis including converter encoding and decoding functions have not previously been investigated thoroughly, and these are key elements in the choice of converter designs for low-noise systems such as bio-optoelectronic sensors. Frequency domain analog front-end models of ADCs are developed to enable the architectural modeling of ADCs. The proposed models can be used for ADC statistically worst-case performance estimation, with stationary random process assumptions on input signals. These models prove able to reveal the architectural advantages of a specific analog-to-digital converter schemes quantitatively, allowing meaningful comparisons between converter designs. The modeling of analog-to-digital converters as communication channels and the ADC functional analysis as encoders and decoders are developed. This work shows that analog-to-digital converters can be categorized as either a decoder-centered design or an encoder-centered design. This perspective helps to show the advantages of nonlinear decoding schemes for oversampling noise-shaping data converters, and a new nonlinear decoding algorithm is suggested to explore the optimum solution of the decoding problem. A case study of decoder-centered and encoder-centered data converter designs is presented by applying the proposed theoretical framework. The robustness and flexibility of the resulting analog-to-digital converters are demonstrated and compared. The electrical and optical sensitivity measurements of a fabricated oversampling noise shaping analog-to-digital converter circuit are provided, and a sensor system-on-a-chip using these ADCs with integrated interferometric waveguides for bio-optoelectronic sensing is demonstrated.

Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond. This work proposes a robust, fault-tolerant scheme to achieve high SFDR in an av- eraging flash A/D converter using comparator chopping. Chopping of comparators in a flash A/D converter was never previously implemented due to lack of feasibility in implementing multiple, uncorrelated, high speed random number generators. This work proposes a novel array of uncorrelated truly binary random number generators working at 1GHz to chop all comparators. Chopping randomizes the residual offset left after averaging, further pushing the dynamic range of the converter. This enables higher accuracy and lower bit-error rate for high speed disk-drive read channels. Power consumption and area are reduced because of the relaxed design requirements for the same linearity. The technique has been verified in Matlab simulations for a 6-bit 1Gsamples/s flash ADC under case of process gradients with non-zero mean offsets as high as 60mV and potentially serious spot offset errors as high as 1V for a 2V peak to peak input signal. The proposed technique exhibits an improvement of over 15dB compared to pure averaging flash converters for all cases. The circuit-level simulation results, for a 1V peak to peak input signal, demon- strate superior performance. The reported ADC was fabricated in TSMC 0.18 ??mCMOS process. It occupies 8.79mm2 and consumes about 400mW from 1.8V power supply at 1GHz. The targeted SFDR performance for the fabricated chip is at least 45dB for a 256MHz input sine wave, sampled at 1GHz, about 10dB improvement on the 6-bit flash ADCs in the literature.

Thesis (Ph. D.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 153-158).

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

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