Spelling suggestions: "subject:"analógicodigital"" "subject:"analogdigital""
151 |
Photonic analog-to-digital coonversion using a robust symmetrical number system /Fisher, Adam S. January 2005 (has links) (PDF)
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2005. / Thesis Advisor(s): Phillip E. Pace. Includes bibliographical references (p. 55). Also available online.
|
152 |
Study of a high frequency electro-optic beam deflector utilizing reflection-based velocity matchingRenkoski, Timothy Eli. January 2004 (has links)
Thesis (M.S.)--University of Missouri-Columbia, 2004. / Typescript. Includes bibliographical references (leaves 85-89). Also available on the Internet.
|
153 |
Design of a 14-bit fully differential discrete time delta-sigma modulator /Nathany, Sumit Kumar. January 2006 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 2006. / Typescript. Includes bibliographical references (leaves 94-97).
|
154 |
Noise coupling techniques in multi-cell delta-sigma modulators /Bonu, Madhulatha. January 1900 (has links)
Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaf 107). Also available on the World Wide Web.
|
155 |
Design of a 14-bit continuous-time Delta-Sigma A/D modulator with 2 5MHz signal bandwidth /Li, Zhimin. January 1900 (has links)
Thesis (Ph. D.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 114-119). Also available on the World Wide Web.
|
156 |
A CAD tool for analog and mixed signal CMOS circuits /Kasturi, Prasan. January 2006 (has links)
Thesis (Ph. D.)--University of Rhode Island, 2006. / Includes bibliographical references (leaves 124-127).
|
157 |
Design of high-speed power-efficient SAR-type ADCsZhong, Jian Yu January 2017 (has links)
University of Macau / Faculty of Science and Technology / Department of Electrical and Computer Engineering
|
158 |
Trellis decoding of Reed Solomon and related linear block codesButtner, Werner Heinrich 20 December 2006 (has links)
Please read the abstract in the section 00front of this document / Dissertation (M Eng (Electronic Engineering))--University of Pretoria, 2006. / Electrical, Electronic and Computer Engineering / unrestricted
|
159 |
A Highly Digital VCO-Based ADC With Lookup-Table-Based Background CalibrationLi, Sulin 02 August 2019 (has links)
CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on "split ADC" architecture. Each of the two split channels, ADC "A" and "B", contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs' sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADC’s LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate).
|
160 |
Micro-electro-mechanical Resonator-Based Digital and Interface Elements for Low Power Circuitszou, xuecui 11 1900 (has links)
The interest in implementing energy-efficient digital circuits using micro and
nanoelectromechanical resonator technology has increased significantly over the last
decade given their lower energy consumption in comparison to complementary metal
oxide-semiconductor circuits. In this thesis, multiple circuit designs based on micro and
nanoelectromechanical beam resonators are presented. These circuits include a nano
resonator-based flash style analog-to-digital converter, a 4-bit digital-to-analog
converter, and a micro-resonator-based 7:3 counter, all among the key building blocks
of a microcomputing system. Simulations and experimental results were obtained for all
circuits. In general, the proposed circuits based on nanoelectromechanical resonators
show up to 90% reduction in energy consumption compared to their complementary
metal-oxide-semiconductor counterparts in MHz operation speeds, fulfilling
requirements for many applications such as Internet of Things and biomedical devices.
|
Page generated in 0.0522 seconds