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All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital ConvertersDavid, Christopher Leonidas 27 April 2010 (has links)
The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
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A 16-b 10Msample/s Split-Interleaved Analog to Digital ConverterCroughwell, Rosamaria 25 August 2007 (has links)
"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The ‘split ADC’ is a new concept that allows the use of a deterministic, digital, self calibrating algorithm. In this approach, an ADC is split into two paths, producing two output codes from the same input sample. The difference of these two codes is used as the calibration signal for an LMS error estimation algorithm that drives the difference error to zero. The ADC is calibrated when the codes are equal and the output is taken as the average of the two codes. The ‘split’ ADC concept and interleaved architecture are combined in this IC design to form the core of a high speed, high resolution, and self-calibrating ADC system. The dual outputs are used to drive a digital calibration engine to correct for the channel mismatch errors. This system has the speed benefits of interleaving while maintaining high resolution. The hardware for the algorithm as well as the ADC can be implemented in a standard 0.25um CMOS process, resulting in a relatively inexpensive solution. This work is supported by grants from Analog Devices Incorporated (ADI) and the National Science Foundation (NSF). "
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RF Frontend for Spectrum Analysis in Cognitive RadioJayaraman, Karthik January 2014 (has links)
Advances in wireless technology have sparked a plethora of mobile communication standards to support a variety of applications. FCC predicts a looming crisis due to the exponentially growing demand for spectrum and it recommends to increase the efficiency of spectrum utilization. Cognitive Radio (CR) is envisioned as a radio technology which detects and exploits empty spectrum to improve the quality of communication. Spectrum analyzer for detecting spectrum holes is a key component required for implementing cognitive radio. Mitola's vision of using an RF Analog-to-Digital (ADC) to digitize the entire spectrum is not yet a reality. The traditional spectrum analysis technique based on a RF Front end using an LO Sweep is too slow, making it unsuitable to track fast hopping signals. In this work, we demonstrate an RF Frontend that can simplify the ADC's requirement by splitting the input spectrum into multiple channels. It avoids the problem of PLL settling by incorporating LO synthesis within the signal path using a concept called Iterative Down Converter. An example 0.75GHz-11.25GHz RF Channelizer is designed in 65nm Standard CMOS Process. The channelizer splits the input spectrum (10.5GHz bandwidth) into seven channels (each of bandwidth 1.5GHz). The channelizer shows the ability to rapidly switch from one channel to another (within a few ns) as well as down-converting multiple channels simultaneously (concurrency). The channelizer achieves a dynamic range of 54dB for a bandwidth of 10.5GHz, while consuming 540mW of power. Harmonic rejection mixer plays a key role in a broadband receiver. A novel order scalable harmonic rejection mixer architecture is described in this research. A proof-of-principle prototype has been designed and fabricated in a 45nm SOI technology. Experimental results demonstrate an operation range of 0.5GHz to 1.5GHz for the LO frequency while offering harmonic rejection better than 55dB for the 3rd harmonic and 58dB for the 5th harmonic across LO frequencies. While cognitive radio solves the spectrum efficiency problem in frequency domain, the electronic beam steering provides a spatial domain solution. Electronic beam forming using phased arrays have been claimed to improve spectrum efficiency by serving more number of users for a given bandwidth. A LO path phase-shifter with frequency-doubling is demonstrated for WiMAX applications.
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Compressive Sampling as an Enabling Solution for Energy-Efficient and Rapid Wideband RF Spectrum Sensing in Emerging Cognitive Radio SystemsYazicigil, Rabia Tugce January 2016 (has links)
Wireless systems have become an essential part of every sector of the national and global economy. In addition to existing commercial systems including GPS, mobile cellular, and WiFi communications, emerging systems like video over wireless, the Internet of Things, and machine-to-machine communications are expected to increase mobile wireless data traffic by several orders of magnitude over the coming decades, while natural resources like energy and radio spectrum remain scarce. The projected growth of the number of connected nodes into the trillions in the near term and increasing user demand for instantaneous, over-the-air access to large volumes of content will require a 1000-fold increase in network wireless data capacity by 2020. Spectrum is the lifeblood of these future wireless networks and the ’data storm’ driven by emerging technologies will lead to a pressing ’artificial’ spectrum scarcity.
Cognitive radio is a paradigm proposed to overcome the existing challenge of underutilized spectrum. Emerging cognitive radio systems employing multi-tiered, shared-spectrum access are expected to deliver superior spectrum efficiency over existing scheduled-access systems; they have several device categories (3 or more tiers) with different access privileges. We focus on lower tiered ’smart’ devices that evaluate the spectrum dynamically and opportunistically use the underutilized spectrum. These ’smart’ devices require spectrum sensing for incumbent detection and interferer avoidance. Incumbent detection will rely on database lookup or narrowband high-sensitivity sensing. Integrated interferer detectors, on the other hand, need to be fast, wideband, and energy efficient, while requiring only moderate sensitivity.
These future 'smart' devices operating in small cell environments will need to rapidly (in 10s of μs) detect a few (e.g. 3 to 6) strong interferers within roughly a 1GHz span and accordingly reconfigure their hardware resources or request adjustments to their wireless connection consisting of primary and secondary links in licensed and unlicensed spectrum.
Compressive sampling (CS), an evolutionary sensing/sampling paradigm that changes the perception of sampling, has been extensively used for image reconstruction. It has been shown that a single pixel camera that exploits CS has the ability to obtain an image with a single detection element, while measuring the image fewer times than the number of pixels with the prior assumption of sparsity. We exploited CS in the presented works to take a ’snapshot’ of the spectrum with low energy consumption and high frequency resolutions.
Compressive sampling is applied to break the fixed trade-off between scan time, resolution bandwidth, hardware complexity, and energy consumption. This contrasts with traditional spectrum scanning solutions, which have constant energy consumption in all architectures to first order and a fixed trade-off between scan time and resolution bandwidth. Compressive sampling enables energy-efficient, rapid, and wideband spectrum sensing with high frequency resolutions at the expense of degraded instantaneous dynamic range due to the noise folding.
We have developed a quadrature analog-to-information converter (QAIC), a novel CS rapid spectrum sensing technique for band-pass signals. Our first wideband, energy-efficient, and rapid interferer detector end-to-end system with a QAIC senses a wideband 1GHz span with a 20MHz resolution bandwidth and successfully detects up to 3 interferers in 4.4μs. The QAIC offers 50x faster scan time compared to traditional sweeping spectrum scanners and 6.3x the compressed aggregate sampling rate of traditional concurrent Nyquist-rate approaches. The QAIC is estimated to be two orders of magnitude more energy efficient than traditional spectrum scanners/sensors and one order of magnitude more energy efficient than existing low-pass CS spectrum sensors.
We implemented a CS time-segmented quadrature analog-to-information converter (TS-QAIC) that extends the physical hardware through time segmentation (e.g. 8 physical I/Q branches to 16 I/Q through time segmentation) and employs adaptive thresholding to react to the signal conditions without additional silicon cost and complexity. The TS-QAIC rapidly detects up to 6 interferers in the PCAST spectrum between 2.7 and 3.7GHz with a 10.4μs sensing time for a 20MHz RBW with only 8 physical I/Q branches while consuming 81.2mW from a 1.2V supply.
The presented rapid sensing approaches enable system scaling in multiple dimensions such as ADC bits, the number of samples, and the number of branches to meet user performance goals (e.g. the number of detectable interferers, energy consumption, sensitivity and scan time).
We envision that compressive sampling opens promising avenues towards energy-efficient and rapid sensing architectures for future cognitive radio systems utilizing multi-tiered, shared spectrum access.
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Power reduction techniques for CMOS current mode pipelined ADCs. / CUHK electronic theses & dissertations collectionJanuary 2007 (has links)
In addition, we can further reduce the power consumption by reducing the number of interconnects. We propose to use a quaternary (4-level) logic output to replace the binary (2-level) logic output, which will reduce the number of interconnect by half. A 6-bit current mode analog-to-quaternary converter (AQC) test chip is designed with special current mode quaternary logic functions. / The power reduction techniques are carried out in both circuit and system levels. At the circuit level, a new sub-stage design using voltage comparator is proposed to reduce power consumption without any performance degradation. At the system level, we observe that the signal-to-noise ratio (SNR) of a current mode pipelined ADC is proportional to the input current level, and the SNR of a pipelined ADC is dominated by the first few stages. Thus, it is possible to reduce the power consumption without significantly degrading the SNR by gradually reducing the current level of each stage along the pipeline. A 12-bit CMOS current mode pipelined ADC test chip is designed with a 0.35mum CMOS digital process. The measured signal-to-noise and distortion ratio (SNDR), spurious free dynamic range (SFDR) and total harmonic distortion (THD) are 64.90dB, 67.79dB and -67.02dB, respectively. The effective number of bit (ENOB) achieved is 10.49-bit and the calculated FOM is 1.31pJ, which has the lowest power consumption among reported current mode ADCs. / The supply voltage of advanced CMOS technology is reduced to 1V or less. It is very difficult to design high performance analog circuit at this supply voltage because of the limited dynamic range. One possible solution is to use current mode circuit technique which is less sensitive to the limited dynamic range. Moreover, current mode circuit is more suitable for low voltage applications compare to the conventional voltage mode circuit. This research uses analog-to-digital converter (ADC) as a vehicle to investigate current mode design techniques with a main focus on power reduction. / Chan Chi Hong. / "September 2007." / Adviser: C. F. Chan. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4923. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.
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Design techniques for low voltage wideband delta-sigma modulator. / CUHK electronic theses & dissertations collection / Digital dissertation consortiumJanuary 2010 (has links)
Finally, another new 0.5V fully differential wideband amplifier, which can be used in the wideband modulator, has been proposed. The gate-input two-stage amplifier employs a DC common-mode feedback circuit that uses a Miller-amplified capacitor for its frequency compensation. With the proposed technique, the power consumption of the low-voltage amplifier is drastically reduced. / Furthermore, a new dynamic CM level shifting technique for low-voltage CT delta-sigma modulators that employ a return-to-open feedback DAC is reported in the thesis. The technique maintains a stable CM level at the amplifier's inputs for this type of modulators. Simulation results show that it improves the modulator's SNDR by 11%. / In this thesis, we present research works on developing a low-voltage delta-sigma modulator with a wide signal bandwidth. Specifically, a 0.5V complex low-pass continuous-time (CT) third-order delta-sigma modulator that has a single-sided signal bandwidth of 1MHz, targeting for application in Bluetooth receivers, is presented without using any internal voltage boosting techniques which are potentially harmful to the reliability of the device. The wide bandwidth of the modulator at this low supply voltage is enabled by a special common-mode (CM) level arrangement in the system level and by new low-voltage amplifies. Realized in a 0.13mum CMOS process the proposed modulator achieves a 61.9-dB peak signal-to-noise-and-distortion ratio at the nominal supply of 0.5V with 3.4mW consumption, and occupies an active area of 0.9mm2. The modulator achieves the best figure-of-merit among its class. / The development of low-voltage design techniques for analog circuits has recently received a lot of attention due to the continuous shrinking of the supply voltage in modern CMOS technologies, which is projected to reduce to 0.5V for low power applications within ten years in the International Technology Roadmap for Semiconductor. This thesis focuses on developing circuit techniques for low-voltage delta-sigma modulator, a functional block that is widely used in mixed-signal integrated circuits. Several delta-sigma modulators operating at supply voltages below 0.9V have been reported in the open literature. However, none of them supports a signal bandwidth wider than 100kHz with a reasonable performance. / He, Xiaoyong. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 104-111). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.
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A High Speed Sigma Delta A/D-Converter for a General Purpose RF Front End in 90nm-TechnologyÖresjö, Per January 2007 (has links)
<p>In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers.</p><p>The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.</p>
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High-performance delta-sigma analog-to-digital convertersda Silva, Jose Barreiro 14 July 2004 (has links)
Graduation date: 2005
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A study of basic building blocks of analog-to-digital delta-sigma modulatorsGuo, Yuhua 09 January 2004 (has links)
In this thesis, a novel Direct-Charge-Transfer (DCT) integrator structure is
proposed, which can settle much faster than regular switch-capacitor integrators. A
new Spread-Spectrum Dynamic Element Matching (SS-DEM) algorithm is also
introduced, which can effectively spread or shape the nonlinearity error of multi-bit
DAC in the feedback path, thus improve the SNDR and THD performance of overall
delta-sigma modulators. A three-bit quantizer design example is presented, which is
embedded in a MASH2-0 structure delta-sigma modulator prototype and has been
fabricated in AMI CMOS 1.5μm technology. Testing results indicate this quantizer
works well. / Graduation date: 2004
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Design techniques for low-voltage analog-to-digital converterChang, Dong-Young 15 November 2002 (has links)
Continuous process scale-down and emerging markets for low-power/low-voltage mobile
systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the
building blocks for analog signal processing and will encounter severe overdrive problems when
operating at low-voltage conditions. There are several well-known techniques to bypass the
problem. These approaches include: (1) The clock boosting schemes (e.g. 2VDD clock signal)
which cannot be used in submicron low-voltage CMOS processes as gate oxide can only tolerate
the technology's maximum voltage (VDD). (2) The use of scaled/lower threshold transistors, which
are not always scalable to very low voltage supplies as it could suffer from an unacceptable
amount of leakage current (e.g. the switch may not be fully turned off). (3) The use of
bootstrapped clocking, which has added loading and possible reliability issues. (4) The switched-opamp
(SO) technique which is fully compatible with low-voltage submicron CMOS processes
but the operating speed limited due to slow transients from the opamp being switched off and on.
In this thesis, the Opamp-Reset Switching Technique (ORST) topology is proposed for
low-voltage operation. Instead of opamps being turned on and off as in the switched-opamp
technique, the sourcing amplifier is placed in the unity-gain reset configuration to provide reset
level at the output. In this way, high-speed operation is possible. The technique is applied to two
ADCs as examples of low-voltage design.
The first design is a 10-bit 25MSPS pipelined ADC using pseudo-differential structure. It
is fabricated in a 0.35-��m CMOS process. It operates at 1.4V and consumes 21mW of total power.
The second design is a two-stage algorithmic ADC with highly linear input sampling circuit. In
addition to the low-voltage design techniques used in the pipelined ADC, radix-based digital
calibration technique for multi-stage ADC is also proposed. The ADC uses a 0.18-��m CMOS
technology. It operates at 0.9V supply with total power consumption of 9mW. Experimental
results show that the proposed calibration technique reduces spurious free dynamic range from
47dB to 75dB and improves signal-to-noise and distortion ratio from 40dB to 55dB after
calibration. / Graduation date: 2003
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