<p>In order to perform the production testing of the video quality of manufactured set-top-boxes for digital television, an FPGA-based measurement system is designed. Background on sampling and video signals are given, as well as the requirements given by Motorola. From this, a design is proposed and implemented. The demonstrator works as planned and shows good performance in regards to signal to noise ratio and differential gain. The implemented digital communication protocols, such as USB and I2C, also work as expected.</p><p>The main conclusion from this thesis is that implementing video test systems using FPGA is a good approach offering many advantages compared to commercial video measurement instruments or plug-in cards for PCs.</p>

Thesis (Ph. D.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 153-158).

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

In this thesis, a time-based oversampling sigma-delta analog-to-digital converter (ADC) architecture is introduced. This system uses time, instead of voltage, as the analog variable for it quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital pulse. The sigma-delta loop integrator, comparator, and subtractor are all time-based circuits and implemented by using only digital gates. The only voltage-based circuit is voltage-to-time Converter (VTC) which requires only a current source. No amplifier is required in the entire circuit. As a proof of concept, the simulation results for a prototype ADC incorporating this time-based sigma-delta ADC architecture is presented. / text

In order to perform the production testing of the video quality of manufactured set-top-boxes for digital television, an FPGA-based measurement system is designed. Background on sampling and video signals are given, as well as the requirements given by Motorola. From this, a design is proposed and implemented. The demonstrator works as planned and shows good performance in regards to signal to noise ratio and differential gain. The implemented digital communication protocols, such as USB and I2C, also work as expected. The main conclusion from this thesis is that implementing video test systems using FPGA is a good approach offering many advantages compared to commercial video measurement instruments or plug-in cards for PCs.

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

The objective of this Master's thesis was to design and implement a low power Analog to Digital Converter (ADC) used for sensor measurements. In the complete measurement unit, in which the ADC is part of, different sensors will be measured. One set of these sensors are three strain gauges with weak output signals which are to be pre-amplified before being converted. The focus of the application for the ADC has been these sensors as they were considered a limiting factor. The report describes theory for the algorithmic and incremental converter as well as a hybrid converter utilizing both of the two converter structures. All converters are based on one operational amplifier and they operate in repetitive fashions to obtain power efficient designs on a small chip area although at low conversion rates. Two converters have been designed and implemented to different degrees of completeness. One is a 13 bit algorithmic (or cyclic) converter which uses a switching scheme to reduce the problem of capacitor mismatch. This converter was implemented at transistor level and evaluated separately and to some extent also with sub-components. The second converter is a hybrid converter using both the operation of the algorithmic and incremental converter to obtain 16 bits of resolution while still having a fairly high sample rate.

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Analog-to-digital converters (ADCs) are required in almost all signal processing and communication systems. They are often the most critical components, since they tend to determine the overall system performance. Hence, it is important to determine their performance limitations and develop improved realizations. One of the most challenging tasks for realizing software defined radio (SDR) is to move ND conversion as close to the antenna as possible, this implies that the ADC has to sample the incoming signal with a very high sample rate (over 100 MSample/s) and with a very high resolution (14 -to -16 bits). To design and implement AID converters with such high performance, it is necessary to investigate new designing techniques. The focus in this work is on a particular type of potentially high-performance (high-resolution and highspeed) analog-to-digital conversion technique, utilizing filter banks, where two or more ADCs are used in the converter array in parallel together with asymmetric filter banks. The hybrid filter bank analog-todigital converter (HFB ADC) utilizes analog filters (analysis filters) to allocate a frequency band to each ADC in a converter array and digital synthesis filters to reconstruct the digitized signal. The HFB improves the speed and resolution of the conversion, in comparison to the standard time-interleaving technique by attenuating the effect of gain and phase mismatches between the ADCs. Many of the designs available in the literature are compromising between some metrics: design complexity, order of the filter bank (computation time) and the sharpness of the frequency response rolloff (the transition from the pass band to the stop band). In this dissertation, five different classes of near perfect magnitude reconstruction (NPMR) continuoustime hybrid filter banks (CT HFBs) are proposed. In each of the five cases, two filter banks are designed; analysis filter bank and synthesis filter bank. Since the systems are hybrid, continuous time IlR filter are used to implement the analysis filter bank and digital filters are used for the synthesis filter bank. To optimize the system, we used a new technique, known in the literature as frequency response masking (FRM), to design the synthesis filter bank. In this technique, the sharp roll-off characteristics can be achieved while keeping the complexity of the filter within practical range, this is done by splitting the filter into two filters in cascade; model filter with relaxed roll-off characteristics followed by a masking filter. One of the main factors controlling the overall complexity of the filter is the way of designing the model filter and that of designing the masking filter. The dissertation proposes three combinations: use of HR model filter and IlR masking filter, HR model filter/FIR masking filter and FIR model filter/FIR masking filter. To show the advantages of our designs, we considered the cases of designing the synthesis filter as one filter, either FIR or IlR. These two filters are used as base for comparison with our proposed designs (the use of masking response filter). The results showed the following: 1. Asymmetric hybrid filter banks alone are not sufficient for filters with sharp frequency response roll-off especially for HR/FIR class. 2. All classes that utilize FRM in their synthesis filter banks gave a good performance in general in comparison to conventional classes, such as the reduction of the order of filters 3. HR/HR FRM gave better performance than HR/FIR FRM. 4. Comparing HR/HR FRM using FIR masking filters and HR/IIR FRM using IIR masking filters, the latter gave better performance (the performance is generally measured in terms of reduced filter order). 5. All classes that use the FRM approach have a very low complexity, in terms of reduced filter order. Our target was to design a system with the following overall characteristics: pass band ripple of -0.01 dB, stop band minimum attenuation of - 40 dB and of response roll-off of 0.002. Our calculations showed that the order of the conventional IIR/FIR filter that achieves such characteristics is aboutN =2000. Using the FRM technique, the order N reduced to aboutN = 244, N = 179 for IIRJFIR and IIR/IIR classes, respectively. This shows that the technique is very effective in reducing the filter complexity. 6. The magnitude distortion and the aliasing noise are calculated for each design proposal and compared with the theoretical values. The comparisons show that all our proposals result in approximately perfect magnitude reconstruction (NPMR). In conclusion, our proposal of using frequency-response masking technique to design the synthesis filter bank can, to large extent, reduce the complexity of the system. The design of the system as a whole is simplified by designing the synthesis filter bank separately from the design of the analysis filter bank. In this case each bank is optimized separately. This implies that for SDR applications we are proposing the use of the continuous-time HFB ADC (CT HFB ADC) structure utilizing FRM for digital filters. / Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2005.

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